為了滿足下一世代半導體和電子產品的複雜設計所需，積體電路現今已經發展成為單晶片系統( System on Chip , SOC )，在單晶片系統架構中，需要處理包含數位訊號、類比訊號以及混合訊號，在設計過程中，設計者必須採取各種方式對晶片的邏輯功能進行驗證( Function Verification )，然而在傳統的設計流程中，類比電路以及數位電路，採用不同的設計以及驗證流程，使得系統整合與驗證變得非常困難，至今也尚未有一套標準的EDA 工具可以支援混合訊號系統的驗證。為了找出一套適用於類比電路系統級驗證的仿真方法，我們利用波動數位濾波器(Wave Digital Filter, WDF)將類比電路對映到數位電路上，最後將數位電路放入FPGA 中進行仿真，本篇論文將提出一套有效率以及可靠的自動化建構方法將類比電路轉換成波動數位濾波器架構，並解決轉換過程中會遇到的困難及瓶頸，最後在映射到數位電路前，為了找出最佳的關鍵路徑，我們將波動數位濾波器樹狀結構進行排程，以達到最佳效能。由實驗結果來看，本論文提出的方法確實有效的解決了WDF 轉換的問題，並成功地縮短了電路的延遲路徑。;Nowadays, system-on-chip (SOC) designs become the mainstream of integrated circuits (ICs) to satisfy the customer demand for high-complexity electronic products. For SOC designs, it is common to deal with both digital signals and analog signals simultaneously. During the design process, designers have to ensure the function correctness through different functional verification flows. However, it is very difficult to simulate digital and analog circuits together in traditional design flows due to their different design approaches. Therefore, there is still no practical EDA tool to support the verification of mixed-signal systems.
In order to develop an emulation flow for analog circuits, we adopt Wave Digital Filter (WDF) theorems to transform analog behaviors into digital circuits, which can be put into FPGA for fast hardware emulation. In this thesis, an automatic transformation flow is proposed to solve the translation issues from circuit netlist to its corresponding WDF structure, with optimized tree height and number of adaptors. Furthermore, a dedicated scheduling algorithm is also proposed for the WDF tree structure to reduce the critical path and improve the emulation performance. As shown in the experimental results, the proposed algorithm is able to solve the automatic transformation issues for WDF structures and successfully reduce their critical path delay.