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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/72249


    Title: 使用電流路徑操作技術之無巴倫差動輸出倍頻器;A Balun-Less Frequency Multiplier with Differential Output by Current Flow Manipulation
    Authors: 吳維旻;Wu,Wei-Min
    Contributors: 電機工程學系
    Keywords: 毫米波;倍頻器;二倍頻器;接收機前端;mm-Wave;Frequency Multiplier;Frequency Doubler;RFE
    Date: 2016-08-22
    Issue Date: 2016-10-13 14:34:50 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本篇論文提出了一個倍頻器無須額外的巴倫即可提供差動輸出之電路架構與技術。此架構在倍頻器輸入端之多功能網路,其操作此倍頻器核心電路周圍之電流流向,確保差動輸出兩端電流是在同一電流路徑下產生的。此多功能網路在基頻fin時為一匹配網路而在所需輸出諧波項頻率Nfin時為一通帶停止濾波器,阻止所需N倍頻輸出電流回流至倍頻器輸入端,此外,倍頻器中電晶體本身之米勒電容Cgd將會提升濾波器抑制輸出電流回流之能力,降低輸入端之多功能網路設計困難度。由於輸出電流有著相同的相位與大小,分別流入與流出相同輸出負載,因此倍頻器能完美的保持差動輸出。實作上此倍頻器利用90奈米互補式金氧半導體製程設計在60-GHz的頻率以驗證此差動輸出的架構理論。此倍頻器量測之輸出相位與功率差分別只有0.5度與0.2 dB,此時在60-GHz之輸出頻率的轉換增益為-5.5 dB,3dB頻寬比例為22.6%,基頻訊號抑制能力在頻寬內都能高於16.3 dB,在偏壓1 V與輸入功率-2 dBm進入電路情況下,功耗只有15.9 mW。
    本篇論文也提出一個整合五級架構之低雜訊放大器、寬頻之LO巴倫、單平衡架構之混頻器與前述提出之倍頻器之94-GHz接收機前端電路。利用90奈米互補式金氧半導體製程實現此電路,其可在輸出10 MHz之IF頻率下提供模擬電壓轉換增益26.3 dB與雙邊頻帶雜訊12.2 dB,在偏壓1 V情況下只有20.4 mW之功耗。
    ;This thesis presents a balun-less frequency multiplier architecture which can provide differential output without any additional balun required. The architecture manipulates the current flows around the multiplier core to enforce the output currents being generated from the same current loop by introducing a multifunction network at the multiplier input. This network works as an impedance matching network at the input frequency fin while becoming a band-stop filter at the desired output harmonic frequency Nfin for rejecting any N-th harmonic current flowing back to the multiplier input. Moreover, the intrinsic Miller capacitance of the multiplier transistors, Cgd, provides high band-stop rejection which greatly eases the multifunction network design. Hence the multiplier outputs are guaranteed to be perfectly differential as the output currents with same amplitude and phase flow into and out the loads with same impedance, respectively. A 60-GHz frequency doubler (FD) realized in a 90-nm CMOS technology is designed to verify the proposed frequency multiplier architecture. The measured phase and amplitude imbalance of the FD are only 0.5° and 0.2 dB while providing conversion gain of -5.5 dB at the output frequency of 60 GHz. The 3-dB fractional bandwidth is 22.6%. The fundamental rejection is better than 16.3 dB within the bandwidth. The FD consumes 15.9 mW from a 1 V supply as an input signal with -2 dBm power is applied.
    A 94-GHz receiver front-end (RFE) which integrates a five-stage low-noise amplifier, a broadband LO balun, a single-balanced mixer, and a FD adopting the proposed FD architecture is also exhibited in this thesis. Implemented in a 90-nm CMOS technology, the RFE can provide simulated voltage conversion gain of 26.3 dB and double-sideband noise figure of 12.2dB at the IF frequency of 10 MHz while only consuming 20.4 mW from a 1 V supply.
    Appears in Collections:[電機工程研究所] 博碩士論文

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