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    题名: 實現波動數位濾波器架構下之類比仿真器的非線性電晶體模型;Nonlinear Transistor Model for WDF-Based Analog Emulators
    作者: 王章翰;Wang,Chang-Han
    贡献者: 電機工程學系
    关键词: 波動數位濾波器;非線性電晶體模型;類比仿真器;wave digital filter;Nonlinear Transistor Model;Analog Emulator
    日期: 2016-08-22
    上传时间: 2016-10-13 14:34:57 (UTC+8)
    出版者: 國立中央大學
    摘要: 在現今的超大型積體電路設計裡通常同時包含了類比電路與數位電路,隨著
    製程的進步,混合訊號(Analog/mixed-signal)晶片設計的驗證流程越來越複雜並
    且消耗大量時間與精力,這也成為了上市時間的主要瓶頸,因此如何找到可靠的
    對於混合訊號晶片的模擬(Simulation)與仿真(Emulation)變得十分的重要,然而,
    在現有的技術裡並不存在一個完美的類比電路仿真器,為了要發展出可靠的仿真
    流程,我們在這篇論文裡利用了波動數位的轉換規則,它主要是利用入射波與反
    射波來描述電路元件的特性,將連續訊號的類比電路快速且準確的轉換成離散訊
    號的等效數位電路。
    根據波動數位濾波器(WDF, Wave Digital Filter)的理論,幾乎每個類比元件都
    可以ㄧ對ㄧ對映成數位元件,然而,對於非線性元件並沒有一個好的對映模型,
    因此在這篇論文裡,我們提出了一個新的以波動數位濾波器為基礎的非線性
    MOS 元件模型,這個模型在多個電晶體的狀況下可以確保電路的收斂,並且使
    用了查表法讓模擬的結果與HSPICE 一樣具有相當高的準確度,與小訊號模型
    (SSM, Small-signal Model)相比之下,新的非線性模型可以有較少的硬體消耗並且
    具有較高的準確度,除此之外,本篇論文建構了軟體驗證環境,可以用於將SPICE
    netlist 轉換成WDF netlist 後的驗證,還可以評估所建立的非線性模型的準確度,
    並且可以減少發展FPGA 仿真器階段時的除錯時間。;Modern VLSI designs usually contain digital and analog circuits. Due to the
    advanced process technologies, the verification of analog/mixed-signal (AMS)
    integrated circuits (ICs) becomes increasingly expensive and complicated and
    becomes the major bottleneck for Time-to-Market concern. As a result, it is quiet
    important to find a reliable simulation and emulation method for AMS circuits.
    However, a feasible emulation solution doesn’t exist for AMS circuits. In order to
    develop a reliable emulating process, we utilize wave digital principle (WDF), which
    is a fast and accurate method to convert analog circuit into digital circuit, as the
    foundation of this work. This method illustrates the characteristics of circuits by
    incident and reflected waves; in other words, it can transform an analog circuit
    containing continuous signal into equivalent digital circuit containing discrete signal.
    Almost every analog component can be mapped into digital component
    one-by-one by using WDF theory; however, there is no practical solution for
    nonlinear components mapping yet. In this thesis, we propose a new WDF-based
    MOSFET component which can ensure convergence caused by multiple transistors
    and have a high accuracy just as HSPICE by using lookup table approach.
    Furthermore, it also has a higher precision and a lower hardware cost as compared
    with the small-signal model (SSM). A software verification environment is also
    developed to verify the accuracy of WDF netlist transformed from SPICE netlist. It
    plays an important role in the development of WDF emulator by evaluating the
    accuracy of a new nonlinear model; moreover, it will reduce hardware debug time in
    the development of FPGA emulator.
    显示于类别:[電機工程研究所] 博碩士論文

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