用於高壓積體電路佈局最佳化的三階B*-Trees;Three-Level Hierarchical B*-Trees for Layout Optimization of High-Voltage VLSI Circuits

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Title:	用於高壓積體電路佈局最佳化的三階B-Trees;Three-Level Hierarchical B-Trees for Layout Optimization of High-Voltage VLSI Circuits
Authors:	李致緯;Lee,Chih-Wei
Contributors:	電機工程學系
Keywords:	高壓電路;自動化佈局;High-Voltage Circuits;automatic placement;B*-Trees
Date:	2016-08-23
Issue Date:	2016-10-13 14:35:47 (UTC+8)
Publisher:	國立中央大學
Abstract:	現今類比電路設計大多以人工的方式產生佈局，雖然使用類比設計自動化工具可以節省設計工作量，但類比電路眾多的佈局限制仍是類比設計自動化發展的難題。目前存在許多類比元件擺置的相關文獻，然而對於高壓電路晶片擺置的研究卻非常稀少。高壓電路在設計與佈局上的限制都較為複雜，且操作電壓較高且廣，為確保連接高電壓與低電壓等。不同電壓的電晶體於操作過程中不會受到彼此的干擾，電晶體周圍會使用隔離環（isolation ring）包覆以達到保護元件的效果，但是隔離環於電路佈局時卻占大量的面積，有必要開發適當的擺置最佳化演算法，以降低下線成本。考量高壓類比電路的敏感性，於佈局最佳化面積的同時也必須考慮其元件擺置的對稱性及可繞線度等限制，如此更增加高壓類比電路佈局自動化的困難度。本論文提出一個在擺置階段考量高壓類比電路對稱性及其佈局限制的最佳化流程。擺置過程中，會先以P-Cell的方式分析元件的擺放限制與大小，根據萃取到的資訊，在考慮電晶體對稱的條件下不斷地改變電晶體層級及隔離環（isolation ring）層級的擺放位置，藉由改變電晶體的位置使隔離環改變面積及形狀後，再改變隔離環位置使整體面積降至最小。從實驗結果來看，透過演算法擺置元件後，其於節省面積與程式執行的效率都有很不錯的表現。;Currently, the layouts of analog circuits are often generated manually. Although some EDA tools can help to reduce design efforts, the complexity of layout constraints is still a big issue that limits the development of EDA tools. In the literature, there are many works related to the placement of analog circuits. However, few of them are discussing about the placement of high-voltage circuits. Compared with general circuits, the design of high-voltage circuits is more complex with more constraints. Since high-voltage circuits demand higher operating voltages and wider voltage ranges, transistors often require isolation rings around them to protect transistors from disturbing each other. Because isolation rings will occupy large chip area, it is necessary to develop proper EDA tools for the placement optimization with isolation rings to reduce the chip cost. Due to the sensitivity of high-voltage circuits, some additional constraints such as symmetry and routability should be considered during placement stage, which further increases the difficulties of EDA tools. This thesis proposes a placement flow to consider both symmetry constraints and isolation rings for the placement optimization of high-voltage circuits. First, we analyze the size and constraints of the P-cell elements in the original circuits. Following the extracted constraints, we will adjust the location of transistors inside every isolation rings to change the shape of isolation rings. Meanwhile, different shapes of isolation rings will be considered simultaneously during the placement algorithm to optimize the layout area. According to the experimental results, the proposed placement algorithm is able to reduce the chip area for high-voltage designs with isolation rings and still keeps the algorithm efficiency.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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