本論文使用tsmcTM 0.18-um製程來實現收發機中本地振盪源的相關電路；本論文首先將介紹雙頻壓控振盪器的操作機制，再來討論四相位振盪器的產生機制，並設計使用轉導提升之壓控振盪器整合除頻器，最後實現一個具有四相位輸出的鎖相迴路，實作電路的量測結果會用來驗證電路的設計理論。本文內容包含三個電路，內容如下所述： 一、應用四階共振腔與直接注入耦合之雙頻四相位壓控振盪器之研製 本電路利用四階共振腔來切換兩個振盪頻率，使用直接注入耦合來產生四相位的輸出並且使功耗得以減少，低頻段的調頻範圍可以從2.45 ~ 2.7 GHz，高頻段的調頻範圍可以從4.8 ~ 5.2 GHz，低頻段與高頻段的相位雜訊在偏移1 MHz處分別為-116 dBc/Hz與-109 dBc/Hz，電路功耗分別為3.8 mW與5.04 mW，電路的優化指數（FoM）分別為-178 dBc/Hz與-176 dBc/Hz，晶片面積為0.98 × 0.97 mm2。 二、使用轉導提升與電流再利用之壓控振盪器整合除頻器之研製 本電路包含一顆壓控振盪器與電流模式邏輯除頻器(CML Divider)，壓控振盪器的部分使用轉導提升的技術來加大擺幅並降低相位雜訊，壓控振盪器的可調頻率範圍為5.4 ~ 6.2 GHz，除頻器的除頻範圍為2.7 ~ 3.1 GHz，壓控振盪器與除頻器的相位雜訊分別為-116 dBc/Hz與-122.3 dBc/Hz，電路功耗為3.84 與5.3 mW，晶片面積為0.64 × 0.9 mm2。 三、X-band四相位鎖相迴路之研製 本電路包含使用轉導提升技術的四相位壓控振盪器，電流模式邏輯除頻器，單一時脈除頻器(TSPC Divider)，相位頻率檢測器(PFD)、充電汞(CP)、迴路濾波器(Loop Filter)，四相位壓控振盪器採用轉導提升的技術來降低相位雜訊，參考頻率為42MHz，操作頻率在10.75 GHz，整體功耗為54mW，晶片面積為0.92 × 1.03 mm2。 ;The mobile wireless has been developed rapidly in recent years. The demands of faster internet also increase dramatically. Therefore, the high performance RF transceivers are needed. The design goals of the recent RF transceivers are like high data rate, low power consumption and small size. Such as Multi-mode and broadband are used to achieve those target. The local oscillator is a key component in RF transceivers. It usually realized by voltage controlled oscillator (QVCO) or phase locked loop (PLL). This thesis includes a dual-band quadrature voltage controlled oscillator (QVCO), a VCO integrated with divider and a quadrature phase locked loop. All circuits are fabricated in tsmcTM 0.18-m CMOS technology. Chapter 1 is the motivation of the research system standards. And chapter 2 introduces QVCO and presents a dual-band QVCO. The dual-band operation is realized by 4th order resonant without using switches. Direct-Injection coupled technique can reduce power consumption. This design is fabricated in 0.18-μm CMOS technology. The measured low band frequency tuning range is from 2.45 GHz to 2.7 GHz. The high band frequency tuning range is from 4.8 GHz to 5.2 GHz. The phase noise of low band and high band are -116 dBc/Hz and -109 dBc/Hz respectively at 1-MHz offset. The power consumption of low band and high band are 3.8 mW and 5.04 mW respectively. The FoM of low band and high band are -178 dBc/Hz and -176 dBc/Hz respectively. The chip area is 0.98 × 0.97 mm2. Chapter 3 presents a VCO integrated with a frequency divider. Gm-boosted and current-reused technique are used in VCO design. The frequency divider topology is current mode logic divider(CML). The VCO has improved phase noise performance by using gm-boosted technique. This design is fabricated in 0.18-μm CMOS technology. The measured VCO frequency tuning range is from 5.4 GHz to 6.2 GHz. The divider frequency range is from 2.7 GHz to 3.1 GHz. The phase noise of VCO and divider are -116 dBc/Hz and -122.3 dBc/Hz respectively at 1-MHz offset. The power consumption of VCO and divider are 3.8 mW and 5.3 mW respectively. The chip area is 0.64 × 0.9 mm2. Chapter 4 introduces phase-locked loop and present a quadrature phase locked loop. This design includes a QVCO, CML divider, TSPC divider, phase and frequency detector, charge pump and low pass filter. The QVCO utilizes gm-boosted technique to have better phase noise performance. The reference frequency is 42 MHz. The output frequency is 10.75 GHz. The total power consumption is 54 mW. The chip area is 0.92 × 1.03 mm2. Chapter 5 is about conclusion and future works.
