隨著未來在半導體產業上電晶體元件的微縮發展，穿隧式場效電晶體以能帶穿隧方式產生電流，該電晶體僅需低的操作電壓即可使元件運作，且擁有低的次臨限斜率、極好的開關切換特性、在關閉時低的漏電流與低功率損耗等優點，有別於傳統金氧半場效電晶體其載子以飄移-擴散方式來傳導電流，次臨限斜率會被kT/q所限制。III-V族材料的穿隧式場效電晶體因具有比傳統矽材料還低的能隙寬度，而有較高的穿隧機率，達到高的元件導通電流及更低的操作偏壓，固本論文著重於開發III-V族化合物半導體之穿隧式場效電晶體。 本論文使用了同質結構與兩種不同異質結構之III-V族p-i-n摻雜材料磊晶，為了達到穿隧機制需有p+重摻雜的源極與n+重摻雜的汲極。同質結構為砷化銦鎵材料之銦的成分比例佔53%，鎵的比例佔47%；而第一種異質結構為銻砷化鎵/砷化銦鎵，此能隙排列擁有較小的有效穿隧能障，使之能產生較大的導通電流，源極為p+型銻砷化鎵；第二種異質結構為在第一種異質結構的p-i接面處加入6-nm 砷化銦鎵材料形成具口袋式異質結構穿隧式場效電晶體，此能隙排列能使導通電流更加提升。 藉由光學曝光進行微米尺寸穿隧式場效電晶體元件圖形定義，探討不同磊晶材料之導通電流特性。成功製作出具砷化銦鎵口袋式銻砷化鎵/砷化銦鎵之穿隧式場效電晶體元件在汲極長度LD = 2 μm的元件，氧化鋁/氧化鉿EOT為2 nm，閘極電壓VG = 2 V，汲極電壓VD = 0.5 V時，汲極導通電流為11.98 μA/μm。 ;As transistors are scaled-down in the semiconductor industry, it is important to replace MOSFETs for low power application due to the ability to make device work with a lower supply voltage, without increase in OFF state currents. Unlike the MOSFET which uses thermal carrier injection, the TFET utilizes band-to-band tunneling as a source carrier injection mechanism. Advantages of TFETs include excellent switching characteristics, small operating voltage and low power consumption. Since the TFET has a different source carrier injection mechanism than does the MOSFET, it can achieve sub-60-mV/dec subthreshold slope. III-V material based devices with high ON current have been considered. The high tunneling probability due to the narrow and direct bandgap. Therefore, III-V material based TFETs are studied in this thesis. There are three different epitaxy structures used in this study, one homo-junction structure and two different hetero-junction structures. In order to achieve the tunneling operation of n-type TFET, a heavily doped In0.53Ga0.47As is dedicated for source, n+- In0.53Ga0.47As is for drain, and undoped In0.53Ga0.47As is for channel in In0.53Ga0.47As homo-junction structure. The first hetero-junction TFET has a p+ GaAs0.51Sb0.49 source with an intrinsic In0.53Ga0.47As channel and a n+ In0.53Ga0.47As drain. The second hetero-junction TFET is similar to the hetero-junction TFET, with the exception that a 6-nm In0.7Ga0.3As “pocket” is grown next to the source to provide a smaller tunneling barrier. In this study, we use optical lithography and wet etching method to fabricate the micron dimension TFETs. Different epi structures involve in on-stated current were studied for insulators including Al2O3/HfO2 (EOT of 2 nm) by ALD. At room temperature, the characteristics of the hetero-junction TFET with pocket could obtain the maximum on current (Ion) 11.98 μA/μm.
