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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/72304


    Title: 應用於多輸入輸出前編碼系統之通用型矩陣分解運算器之架構設計與硬體實作;Design and Implementation of Generalized Matrix-Decomposition Processor for MIMO Precoding
    Authors: 吳昱奇;Wu,Yu-Chi
    Contributors: 電機工程學系
    Keywords: 多輸入輸出;前編碼;QR分解;特徵值分解;奇異值分解;幾何平均值分解;multiple input multiple output;precoding;QR decomposition;eigen value decomposition;singular value decomposition;geometric mean decomposition
    Date: 2016-08-29
    Issue Date: 2016-10-13 14:38:03 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 5G通訊中能有效提升無線通訊速率的方法有數種,多輸入輸出為最有效的核心概念並且許多技術都被應用於此架構上,而前編碼技術在其中扮演非常重要的角色,前編碼技術包含了不只發送端還必須要有接收端的緊密配合,在發送端前編碼器需要將訊號使用前編碼矩陣的資料來做發送,在接收端等化器一方面需要使用解碼矩陣的資料來還原接收訊號,一方面還必須考慮硬體的複雜度,同時還得做出快速且準確的通道估測以及效率高錯誤率低的解碼,這些技術都相當倚賴精確度高且多樣性高的通道矩陣分解處理器,本篇論文提出了一個通用型的通道矩陣分解處理器的架構,能夠支援到4根發送天線對應4根接收天線的多輸入多輸出系統,此外能夠在多輸入輸出系統中對通道矩陣分別分解三種不同矩陣分解法,分別是QR分解、特徵值分解以及幾何平均分解,其中所提出的幾何平均分解的演算法利用現有的穩定吞吐量的基礎做了相當改良,能大幅減少分解時近百分之二十一的CORDIC運算數量;透過簡化硬體的模組分類、單純化資料流,這套硬體能發揮出極大的硬體共用與硬體使用效率,如此除了能加速操作時脈達到21.4 MHz之外同時也增加吞吐量,使QR分解只需花費十二個時脈、特徵值分解平均花費五十以內個時脈,幾何平均分解平均花費三十九個時脈,另外硬體有兩大部分的基本運算單元,互相為鏡像的關係,因為這項特性能在分解通道矩陣時同時還原其基底矩陣,當通道矩陣分解完的時候即可得到相對應的左右基底矩陣,也就是解碼矩陣與前編碼矩陣。;There are several ways to enhance the transmission efficiency of wireless communication in the future 5G. Among them, the multiple-input multiple-output (MIMO) technique is one of the essential solutions. MIMO precoding techniques play an important role recently, which form a close loop that needs joint design of the transmitter side and the receiver side. Several matrix decomposition algorithms are adopted for MIMO precoding. This thesis presents an architecture of a generalized matrix-decomposition processor which can support 4 by 4 MIMO systems. Three different matrix decomposition can be accomplished, including QR decomposition, eigen value decomposition (EVD) and geometric mean decomposition (GMD). The proposed GMD algorithm can reduce almost 21% CORDIC computations during the equalization phase. It takes 12 clock cycles for QRD, less than 50 clock cycles for EVD and about 39 clock cycles for GMD. Two major processing units are designed to generate the decomposed channel matrix, precoding matrix and decoding matrix simultaneously. A total of 16 CORDIC modules are used. The operating frequency achieves 21.4 MHz
    Appears in Collections:[電機工程研究所] 博碩士論文

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