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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/72647


    Title: 使用系統封裝技術實現高頻率射頻能量獵取電路;High-Efficiency RF Energy Harvester Design Using System-In-Package Technique
    Authors: 余銘哲;Yu, Ming-Che
    Contributors: 電機工程學系
    Keywords: 能量獵取電路;系統級封裝;Energy Harvester;SiP
    Date: 2016-10-28
    Issue Date: 2017-01-23 17:09:51 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文提出使用系統封裝實現高頻能量獵取電路的技術,高頻能量獵取電路架構包含輸入阻抗匹配網路、覆晶錫球與整流器電路,其中匹配網路實做於GIPD製程並透過覆晶錫球與0.18-µm CMOS製程的整流器電路整合,0.18-µm CMOS製程提供低臨界電壓(0.2 V)的Native Device,藉由此製程技術可提升整流器的敏感度,GIPD製程提供匹配網路中被動元件相當高的品質因素,使用此方式不只能降低匹配網路損耗,高品質因素的被動元件更能有效的實現輸入訊號源到整流器的輸入阻抗間的高阻抗轉換比,提升匹配網路提供的被動電壓增益,進而大幅提升整體能量獵取電路的效率,本論文中實做三個電路驗證使用系統封裝技術是能有效提升能量獵取電路的效能。
    第一個設計中,將使用系統封裝技術(SiP)與系統級(SoC)晶片做比較,其中系統級晶片製成為0.18-µm CMOS,量測結果顯示,系統封裝技術的能量獵取電路在2.4 GHz下有4.7%的效率,相較於系統級晶片改善了72%.
    第二個設計將透過優化覆晶錫球效率與更換電感布局提升第一個設計的效率,其中覆晶錫球透過加入接地迴路在訊號路徑旁邊,進而降低了接地迴路所造成的阻抗不匹配與額外訊號損耗,透過這個方法可以大幅降低覆晶錫球所造成的損耗。覆晶錫球模擬結果為-0.04 dB,比起第一個晶片中的覆晶錫球有2.85 dB的提升,此外,考慮GIPD圖層設計規則中,金屬圖層間的連接(VIA)必須大於35*35μm2,造成第一顆晶片中的八角型電感的設計受限,進而使用方型電感改善,模擬結果顯示在2.4 GHz下方型電感品質因素從原本八角型電感的22提升到31。量測結果顯示,轉換效率為6.8 %,相較於第一個設計有了1.44倍的提升。
    第三個設計提出雙頻帶能量獵取電路透過在匹配網路之前整合帶通與帶止濾波器實現,透過帶通與帶止濾波器所提供的零點與極點,可以控制通帶與止帶訊號頻率,進而實現雙頻帶匹配的效果,量測敏感度為-13.2/-15.43 dBm 輸入,輸出電壓為1.51/1伏特,分別在0.89 GHz 與2.52 GHz,計算轉換效率為9.55/6.98。
    ;This thesis proposes high-efficiency RF energy harvester (EH) designs using a system-in-package (SiP) technique. The EH is consisted of matching networks, interconnects, and rectifiers. The matching networks are realized on a low-loss Glass-Integrated-Passive-Devices (GIPD) carrier while the rectifiers are implemented in a 0.18-µm CMOS technology. The CMOS chip is flipped and bonded onto the carrier through the interconnects. The native devices with threshold voltage of 0.2 V in the 0.18-µm CMOS technology enable the rectifiers to have high sensitivity. Passive components with high quality factor (Q) provided by the GIPD technology are used to design the matching networks. This not only gives a compact solution, but higher impedance transformation ratio between the source resistance and the rectifier input impedance also becomes feasible, which provides higher voltage gain to greatly enhance the EH efficiency. Three RF EHs are designed in this thesis to demonstrate the benefits of using the SiP technique.
    The performance of the first RF EH is compared with that of a RF EH using a system-on-a-chip (SoC) technique in a 0.18-µm CMOS technology. The measurement result shows that the SiP-based RF EH provides peak efficiency of 4.7% at 2.4 GHz, around 72% improvement as compared with that of the SoC-based one.
    The second RF EH improves the efficiency of the first one by optimizing an interconnect between the chip and the carrier and choosing a better inductor type. By properly designing the gap between the signal and ground bonding pads, the impedance mismatch and the power loss caused by the return path of the interconnect can be minimized. The simulated insertion loss is only -0.04 dB at 2.4 GHz, 2.85 dB improvement over the interconnect used in the first RF EH design. Moreover, considering the design rules of the GIPD technology, octagon inductors employed in the first RF EH design have limited design freedom due to the minimum via size requirement of 35×35 μm2. To avoid the via size issue, the square inductors are chosen, which enhances inductor Q from 22 to 31 at 2.4 GHz as compared with that of octagon ones. The measured efficiency of the second RF EH is 6.8%, 1.44 times better than that of the first RF EH design.
    The third RF EH can provide dual-band operation by integrating additional band-pass and band-stop filters (BPF/BSF) before the matching networks. The proposed BPF/BSF can provide zeros and poles to pass and stop signals, respectively, allowing dual-band operation. The proposed dual-band RF EH can give measured output voltage of 1.51 V and 1.0 V with conversion efficiency of 9.6% and 7.0% at 0.89 and 2.52 GHz, respectively.
    Appears in Collections:[電機工程研究所] 博碩士論文

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