在這篇論文中，我們提出了應用於電阻性非揮發性靜態隨機存取式記憶體之測試及診斷技術。第一部分，我們在電阻性非揮發性靜態隨機存取式記憶體中定義了幾個憶阻器相關之錯誤。運用HSPICE來模擬及分析可能發生於電阻性非揮發性靜態隨機存取式記憶體之瑕疵。第二部分，我們針對電阻性非揮發性靜態隨機存取式記憶體之簡單靜態隨機存取式記憶體錯誤及憶阻器相關錯誤提出類行軍式測試及診斷演算法。為了要評估提出之演算法的錯誤涵蓋率，我們也實現了應用於電阻性非揮發性靜態隨機存取式記憶體之錯誤模擬器。在模擬的結果中，針對特定的錯誤所提出之測試及診斷演算法可以提供100%的錯誤涵蓋率及100%的診斷分辨率。最後，我們也實現了應用於電阻性非揮發性靜態隨機存取式記憶體之可產生類行軍式演算法的內建自我測試電路。根據模擬結果，針對一個256x8位元之非揮發性靜態隨機存取式記憶體，使用TSMC90奈米製程合成之可支援類行軍試演算法的自我測試電路約只需要642個邏輯閘。 ;In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Also, static random access memory (SRAM) typically occupies more than one half of the chip area. Therefore, the static power of a SOC is mainly constituted by the SRAMs. Nonvolatile SRAM has been proposed to preserve data in the power-down mode with the feature of fast power-on speed such that the static power of SRAM can be eliminated in the power-down mode. A nonvolatile SRAM cell consists of a SRAM cell and a nonvolatile storage cell. Therefore, the testing of nonvolatile SRAM is much more difficult than that of SRAM. In this thesis, we propose testing and diagnosis techniques for memristor-based (resistive) nonvolatile SRAMs. Firstly, several memristor-related faults of resistive nonvolatile SRAM are defined. Comprehensive defects are analyzed and simulated for the resistive nonvolatile 8-transistor SRAM using HSPICE. Secondly, we propose March-like test algorithms and diagnosis algorithms for covering simple SRAM faults and the defined memristor-related faults of resistive nonvolatile SRAMs. To evaluate the fault coverage of the proposed test algorithms, we also implement a fault simulator for nonvolatile SRAMs. Simulation and analysis results show that the proposed test and diagnosis algorithms can provide 100% fault coverage and 100% diagnostic resolutions for the targeted faults. Finally, a built-in self-test design which can generate the March-like tests for resistive nonvolatile SRAMs is proposed. Simulation results show that only about 642 gates are needed to support March test algorithms for a 256×8-bit nonvolatile SRAM using TSMC 90nm standard cell library.
