應用於心電訊號壓縮感測之感測器端設計與特徵擷取;Compressed Sensing Encoder Design and Feature Extraction for ECG Signals

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Title:	應用於心電訊號壓縮感測之感測器端設計與特徵擷取;Compressed Sensing Encoder Design and Feature Extraction for ECG Signals
Authors:	黃銘浩;Huang, Ming-Hao
Contributors:	電機工程學系
Keywords:	無線體域網路;心電訊號;離散小波轉換;壓縮感測;Wireless body sensor network;Electrocardiogram;Discrete wavelet transform;Compress sensing
Date:	2017-05-11
Issue Date:	2017-10-27 16:08:55 (UTC+8)
Publisher:	國立中央大學
Abstract:	我們提出應用於無線體域網路(Wireless body sensor network)偵測心電訊號(Electrocardiogram, ECG)之低複雜度壓縮感測技術(Compressed sensing)，本論文主要針對編碼器端(encoder)進行設計。將心電圖經過離散小波轉換(discrete wavelet transform, DWT)，利用在小波域(wavelet domain)上的稀疏特性，以大量的心電訊號資料庫統計轉換後的結果，建立心電訊號轉換後的特性圖，幫助搜尋小波訊號數值較大的代表點。繼而乘上二元稀疏矩陣(binary sparse matrix)將訊號壓縮兩倍，就可以用來無線傳輸。硬體和記憶體設計方面，盡量減少記憶體的使用數量而且讓每個時脈都進行運算，這樣可以降低硬體面積以及運算時間。接著我們將編碼端進行硬體實現，驗證硬體運作功能與演算法相符合之後，利用台積電0.18μmCMOS製程(T18)進行硬體佈局(layout)，驗證DRC和LVS通過後，以手動接線方式將數位和類比的佈局進行整合，完成整個心電感測系統的晶片。數位晶片的部分使用面積(core area)為2.75 mm^2且gate-count為83.8K，電壓輸入1.8V與操作頻率為1.2KHz時，功率消耗為0.718μW。另一方面，我們提出應用於編碼端的心電訊號萃取演算法，參考許多文獻的方法加以改善和整合。用微分(differentiation)和平方(squaring)的運算找出心電圖QRS波群(QRS complex)區域，尋找最大值為R波峰(R peak)，如果搜尋失敗則利用Gabor小波對正(Gabor wavelet correlation)輔助搜尋，再使用Gabor小波轉換萃取QRS波群特性。接著用前兩個心電訊號的已知資訊與可變得臨界值，以複雜度較低的方法搜尋之後的心電圖特性點，此方式可兼具正確性和低運算複雜度。最終比較手動標記和演算法搜尋特性點位置的誤差，相對於其他文獻，效能可得到改善。 ;We present low complexity compressed sensing techniques for monitoring Electrocardiogram (ECG) signals in wireless body sensor network. This thesis focus on the design of the encoder part. First, by discrete wavelet transform (DWT), ECG wavelet shows sparsity in the wavelet domain. We then take adventage of the statistics property of ECG signals in the wavelet domain for searching the most significant nonzero components. Next, with the binary sparse sensing matrix, the compression ratio of 2 is obtained and the quantity of the output signals is reduced to a half. In order to decrease chip area and processing time, we try to reduce the memory size and enhance the hardware efficiency. The design is implemented in 0.18μm CMOS technology. After DRC and LVS verification, the analog layout and digital layout are intergrated to complete the SoC chip. As to our digital signal processing part, the core area is 2.75 mm^2 and the gate-count is 83.8K gates. When input voltage is 1.8V and operating frequency is 1.2KHz, power consumption is 0.718μW. On the other hand, we design ECG feature extraction algorithm. First, the QRS complex region is identified by differentiation and squaring to remove baseline wondering, and then the peak of the result is marked as R peak. If the peak search fails, the Gabor wavelet correlation is adopted at the second step. Also, variable threshold is used according to the adjacent ECG signals to strengthen the feature extraction results with low complexity. Finally compared to the prior works, our proposed scheme shows good detection results.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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