新式薄膜電晶體結合閘極內保護汲極電極之設計;A Novel Thin Film Transistor With Gate Sheltered Drain Design

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/74860

Title:	新式薄膜電晶體結合閘極內保護汲極電極之設計;A Novel Thin Film Transistor With Gate Sheltered Drain Design
Authors:	劉旻嘉;Liu, Min-Jia
Contributors:	電機工程學系
Keywords:	複晶矽薄膜電晶體;不理想效應;場引效汲極(FID)
Date:	2017-07-12
Issue Date:	2017-10-27 16:09:39 (UTC+8)
Publisher:	國立中央大學
Abstract:	複晶矽薄膜電晶體相較於非晶矽薄膜電晶體具有較高的載子遷移率與驅動電流，因此廣泛應用於各種領域上，包含主動式液晶顯示器及三維積體電路，而這項技術被喻為最有希望實現將積體電路建立在玻璃面板(system on panel, SOP)作為控制端與記憶元件。然而元件在汲極端的高電場導致許多不理想效應的發生，例如: 漏電流效應、熱載子效應、扭結效應等。為了改善這些不理想效應，過去的學者提出許多不同的結構去改善元件汲極端的高電場，例如:Offset、Lightly Doped Drain (LDD)、Raised Source/Drain(RSD)以及Field-Induced Drain(FID)等結構。雖然這些結構能有效抑制不理想效應的發生，但也同時增加寄生電阻導致元件開電流下降，或者需要額外的光罩及離子佈值增加製程的複雜度。因此提出一個只需幾種簡單的製程，無需昂貴製程步驟的新式結構成為我們研究的動機。在本文中我們提出一個“新式薄膜電晶體結合閘極內保護汲極電極之設計”，此結構利用在閘極層下方新增一個獨立的汲極電極層，藉由與通道的汲極電極相接在一起形成等電位，可以使的通道與汲極端的接面處電壓差趨近於零，分散通道與汲極端接面處的電場。經由我們使用ISE-TCAD模擬結果顯示，汲極端的高電場與離子化碰撞都有大幅的改善，因此有效降低漏電流，使元件有良好的開關電流比。而在製程方面也不需額外昂貴的製程，故當此元件應用於大面積的顯示器上，對於提升元件與電路效益有極大的幫助。 ;Polycrystalline silicon thin film transistors have been attracted for using in various fields, including active matrix liquid crystal displays (AMLCDs) and 3-D integrated circuits because of their high carrier mobility and driving current. The technology is the promised candidate for the ultimate goal of building fully integrated flat panel display system-on-panel (SOP) as a controller and memory. However, a high electric field (EF) near the channel/drain region causes several undesirable effects, such as large leakage current, kink effect and hot carrier effect in TFT. In order to overcome those drawbacks, previous studies used a lot of structures such as offset, Lightly Doped Drain (LDD)、Raised Source/Drain(RSD) and Field-Induced Drain(FID) to reduce the high electric field in the device. Although many of these structures can effectively reduce the electric field, increase the parasitic resistance is lowered a lot of on-current, or require additional mask ion implantation and increased process complexity and cost. Therefore, we propose a structure which requires only a few simple processes, without requiring expensive processing steps to improve the practical value of this device. In this paper, we propose a structure entitled “A Novel Thin Film Transistor With Gate Sheltered Drain Design”. Its feature owing to add a additional drain electrode underneath the gate layer, and the sheltered drain is connected to the drain electric potential can distribute the electric field near the channel/drain region because of the potential difference is close to zero. According to our simulation results, the high electric field (EF) and impact ionization (IMP) are substantial improved near the channel/drain region and effectively reduce the leakage current which will make the device have a good ON/OFF current ratio. The new structure also without requiring expensive processing steps and it will be beneficial to circuit efficiency when the devices are applying to large area microelectronics by using our new concept devices.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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