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| 題名: | 應用於生醫偵測之類比前端 可調增益放大器設計;Designs of Analog Front-End Amplifier with Programmable Gain for Bio-sensor |
| 作者: | 陳思涵;Chen, Ssu-Han |
| 貢獻者: | 電機工程學系 |
| 關鍵詞: | 類比前端低雜訊放大器;電流重複使用;analog front-end low-noise amplifier;current reusing |
| 日期: | 2017-07-13 |
| 上傳時間: | 2017-10-27 16:09:41 (UTC+8) |
| 出版者: | 國立中央大學 |
| 摘要: | 由於人們越來越注重身體的健康，各種穿戴式生醫電子醫療儀器如雨後春筍般崛起，透過生醫電子醫療儀器的量測生理訊號，依數值來確保生理上的健康。現今增加儀器的可靠度與降低本身的功耗、體積以及成本，均是當今技術的發展趨勢。故本論文將以如何降低功耗與低雜訊為訴求，來達到目的。本論文由兩部分所組成：
第一部分為設計一個應用於生醫訊號之低雜訊低功耗的放大器，使用部分電流輸入對，減小元件使用面積，後面接上可調整增益放大器，以利於使用於不同生理訊號。
第二部分為設計一個應於生醫訊號之低雜訊低功耗的放大器，導入電流重複使用技術(Current-Reusing)，可以抑制其閃爍雜訊、熱雜訊以及功率消耗，後面接上可調整增益放大器，以使用於不同生理訊號。
本論文的電路設計均使用UMC 0.18 μm CMOS 1P6M製程。為了追求低功耗，因此將所有電路的供應電壓設定為1.2 V。第一部份的類比前端放大器在輸入訊號頻率100 Hz、輸入震幅100 μV下，放大器倍率可從42 dB到69 dB均可有效放大。輸入參考雜訊為4.1065 μVrms，其晶片面積占0.82mm*0.95mm，整體晶片功耗為11.67 μW。第二部份的類比前端放大器在輸入訊號頻率100 Hz、輸入震幅100 μV下，放大器倍率可從45 dB到55 dB均可有效放大。輸入參考雜訊為1.981 μVrms，其晶片面積占0.72mm*0.95mm，整體晶片功耗為6.58 μW。
;People pay attention to the health of the body more and more, various bio-medical wearable devices have been launched to measure the physiological signals through the medical electronic equipment for ensuring the health of physical. Recent years, by improving the multi-purpose biomedical instruments, reliability, power consumption, equipment size and cost are essential to today′s circuit design. Particularly, how to reduce the power consumption and low noise is important to achieve the portability.
This thesis consists of two parts, the first part designs a low noise amplifier for bio-medical application using partial current input pair, and it can reduce the size of elements, and it followed by programmable gain amplifier to be used for different physiological signals. In the second part, designs a low noise amplifier for bio-medical application using current-reusing technique that is used to maintain flicker noise and thermal noise to lower level and to keep low power consumption. And it followed by programmable gain amplifier to be used for different physiological signals.
Designs in this thesis are fabricated in the UMC 0.18 μm 1P6M CMOS process. In order to pursue low-power consumption, the supply voltage is all set up as low as 1.2 V. The first circuit is an LNA. When the input signal is 100 μV input amplitude with 100 Hz, the mid-band gain of analog front-end low-noise amplifier can be programmed from 42 dB to 69 dB. The post layout simulation shows that the input-referred noise is 4.1065 μVrms, the chip area is 0.82mm*0.95mm, and the overall chip consumes 11.67 μW. The second circuit is also an LNA. When input signal is 100 μV input amplitude with 100 Hz, the mid-band gain of analog front-end low-noise amplifier can be programmed from 45 dB to 55 dB. The post layout simulation shows that the input-referred noise is 1.981 μVrms, the chip area is 0.72mm*0.95mm, and the overall chip consumes 6.58 μW. |
| 顯示於類別: | [電機工程研究所] 博碩士論文
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