V及D頻段高除頻數注入鎖定除頻器與四相位鎖頻迴路之研製;Design of V- and D-Band High-Division-Ratio Injection-Locked Frequency Dividers and Quadrature Frequency-Locked Loop

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題名:	V及D頻段高除頻數注入鎖定除頻器與四相位鎖頻迴路之研製;Design of V- and D-Band High-Division-Ratio Injection-Locked Frequency Dividers and Quadrature Frequency-Locked Loop
作者:	李昇洺;Li, Sheng-Ming
貢獻者:	電機工程學系
關鍵詞:	V頻段;D頻段;注入鎖定除頻器;四相位;鎖頻迴路;V-band;D-band;Injection-Locked Frequency Divider;Quadrature;Frequency-Locked Loop
日期:	2017-07-26
上傳時間:	2017-10-27 16:10:34 (UTC+8)
出版者:	國立中央大學
摘要:	近年來，對於高速資料傳輸量的需求，促使更多相關毫米波的通訊系統的研究。在現今收發機裡，本地振盪源通常以鎖相迴路來實現。對於收發機而言，本地振盪源需要低功耗及低相位雜訊。毫米波的鎖相迴路裡需要多級的除頻器來提供高除數。本論文主要針對微波注入鎖定技術應用於除頻器及鎖頻迴路，以達到低功耗、低相位雜訊之研究。第二章主要內容為一個V頻段高除數注入鎖定除十頻器之分析、設計及量測結果。第三章為具鎖頻迴路自對準之次諧波注入鎖定振盪器之電路設計與量測結果。最後，第四章為D頻段注入鎖定除四頻器。V頻段高除數注入鎖定除十頻器及具鎖頻迴路自對準之次諧波注入鎖定振盪器採用台積電提供的90 nm互補式金氧半場效電晶體製程(TSMC 90 nm GUTM CMOS)。D頻段注入鎖定除四頻器則是採用台積電提供的40 nm互補式金氧半場效電晶體製程(TSMC 40 nm GUTM CMOS)。　　第二章首先介紹數種除頻器架構及注入鎖定理論。然後提出注入鎖定除五除頻器對鎖定頻寬的理論模型，從理論模型分析得知，鎖定頻寬跟注入器(injector)的元件與注入訊號大小成正比。利用電感最大化諧波項，提升除五及除十除頻器鎖定頻寬。注入鎖定除十除頻器量測鎖定頻寬為4.2 GHz相當於6.8 %比例頻寬，電路直流總功耗為16 mW。　　第三章為具鎖頻迴路自對準之次諧波注入鎖定振盪器。首先介紹理論模型及轉移函數，接著利用ADS(advance design system)軟體進行模擬分析鎖頻迴路，能夠有效率的分析鎖頻迴路系統的開迴路及閉迴路響應。此外，利用提出的理論模型分析比較各種結構頻率合成器之相位雜訊及抖動量。量測的鎖頻範圍為48.8 到51.1 GHz，各個控制電壓的鎖定範圍約為30 MHz，輸出功率大於-11 dBm。當輸出鎖定頻率為49.7 GHz時，距載波偏移1 MHz的相位雜訊為-103.4 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz為124.8 fs。電路直流總功耗為75.4 mW。　　第四章為寬鎖定頻寬及低功耗的D頻段注入鎖定除四除頻器。如同第二章，鎖定頻寬跟注入器(injector)的元件與注入訊號大小成正比。注入鎖定除四除頻器的自由振盪頻率大約為35.8GHz，相位雜訊為-60.9 dBc/Hz。當注入訊號大小為-5 dBm時，量測所得到的鎖定頻寬約為2.5 GHz，從142.5至145GHz。注入訊號為144 GHz時，輸入與輸出距載波偏移100 kHz的相位雜訊分別為-91.3 dBc/Hz及-102.6 dBc/Hz。輸入與輸出訊號源相位雜訊的差值約為12 dB，與理論計算20log4相符。主要電路功耗為2.2 mW。;In recent years, the research of millimeter-wave　transceiver is increasing to serve a vast range of applications for high data rate wireless communication. A phase-lock loop (PLL) is widely used as a local oscillator (LO) in modern communication transceivers. The LO needs low power consumption and low phase noise for frequency synthesis in most of the transceivers. The high-division-ratio divider chain is also needed in a millimeter-wave PLL. This thesis focuses on the millimeter-wave frequency divider and frequency-locked loop (FLL) using an injection-locked technique to achieve low power consumption and low phase noise. Analysis, design and measured results for V-band high-division-ratio divide-by-10 injection-locked frequency divider (ILFD) in Chapter 2. Analysis, design and measured results of the sub-harmonic injection-locked VCO with FLL self-alignment (SILFLL) are presented in Chapter 3. Finally, a D-band ILFD are proposed in Chapter 4. The V-band divide-by-10 ILFD and SILFLL in this thesis are fabricated using TSMC 90 nm GUTM CMOS process. The D-band ILFD is fabricated using TSMC 40 nm GUTM CMOS process. First, several frequency dividers and the injection-locked theory are introduced in Chapter 2. Then, the locking range of divide-by-5 is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. Using harmonic peaking inductor improves the locking range of divide-by-10 and divide-by-5 ILFDs. The proposed V-band divide-by-10 ILFD features a locking range of 4.2 GHz and a 6.9% fractional bandwidth. The power consumption is about 16 mW. A sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 3. First, the theoretical models and transfer functions of FLL are introduced, then using ADS (advance design system) software with system setup analyses FLL. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Furthermore, a theoretical model of the SILFLL is proposed, and used to calculate phase noise and jitter for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 48.8 to 51.1 GHz and locking range for each control voltage is about 30 MHz. The measured output power is higher than -11 dBm over the range. When the injection-locked output frequency is 49.7 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -103.4 dBc/Hz and 124.8 fs, respectively. The total power consumption is about 75.4 mW. In Chapter 4, we proposed a D-band wide locking range divide-by-4 ILFD with low power consumption. The locking range is proportional to the device size of the injectors and the amplitude of the injection signal like in Chapter 2. The free-running oscillation frequency of the proposed ILFD is about 35.8 GHz and phase noise is -60.9 dBc/Hz. The measured locking range is about 2.5 GHz from 142.5 to 145 GHz with an input power -5 dBm. When the input signal is 144 GHz, the measured input and output phase noises at 100 kHz offset are respectively -91.3 and -102.6 dBc/Hz. The phase noise difference between input and output is about 12 dB, and it agrees with the theoretical calculation (20log4). The core power consumption is about 2.2 mW.
顯示於類別:	[電機工程研究所] 博碩士論文

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