| 摘要: | 本論文呈現前端收發機之子電路，包含兩個版本的功率放大器、低雜訊放大器、以及二極體混波器。在每個電路的分析中，我們描述了設計的細節，並闡述如何透過推拉式模擬、最大可用增益模擬以及直流特性分析等等來訂定合理的電路設計目標。本論文包含兩大部分，分別為前端收發機之接收端以及發送端。
首先，我們呈現低雜訊放大器以及二極體混波器的設計，這兩個電路是接收端重要的兩個子電路。本設計是使用穩懋ED模態0.15微米製程。電路的有效操作頻帶範圍是從25 GHz到40GHz，並且訂定38 GHz為電路中心頻率。低雜訊放大器在140 mW的直流功耗下的增益高達30 dB。另一方面，二極體混波器在10 dBm的本地振盪驅動源的情況下，表現出的增益(損耗)約為-6 dB。特別注意，二極體混波器受益於本身被動的設計，直流功耗甚小。
在功率放大器的設計中，我們訂定了飽和輸出功率為1 W的設計目標，並借助於穩懋氮化鎵製程，希望能設計出能操作於Ka頻帶以及Ku頻帶的功率放大器。然而，Ka頻帶功率放大器因為積熱的關係，導致電路無法正常運作，也造就了我們想更進一步設計較低頻的Ku頻帶功率放大器契機。Ku頻帶功率放大器在10 GHz到15 GHz頻帶間有15 dB的增益，並且有29 dBm飽和輸出功率的成果。
最後，我們藉由台積電40奈米CMOS製程，設計了W頻帶電路設計，並訂定了中心頻率為94 GHz的設計目標，然而因為在該頻帶嚴重的寄生效應、以及較大的匹配電路和被動元件損耗的影響下，這個版本的功率放大器並未成功運作，而相關的除錯方式和電磁模擬方法，我們也會詳細呈現於論文第四章。
本論文完成了前端收發機內除了天線及開關的各個子電路，此外，低雜訊放大器以及二極體混波器已經整合成單一晶片並送出製作，在未來的研究方向會將整合的晶片作完整的量測並分析，期待未來的結果能夠符合收發機的實際應用。
;In this paper, we present each block diagrams of front-end communication, including two versions of power amplifiers (PAs), a low noise amplifier (LNA) and a diode mixer in detail. To make our design goals achievable, we must consult load-pull, maximum available gain, and I-V curve and so on simulations carefully. There are mainly two parts of this paper, including receiver and transmitter of front-end communication system.
First, we present LNA and the diode mixer is design, which are important block diagrams of receiver. These two circuits are designed in operating frequency between 25 GHz and 40 GHz with center frequency at 38 GHz. They are design in process of WIN ED-Mode 0.15 μm. The performance of LNA achieve up to 30-dB gain with about 140-mW DC power consumption. On the other hand, the diode mixer shows up to -6- dB conversion gain (or conversion loss) with 10 dBm local oscillator (LO) driving power. Note that there is no DC power consumption in the diode mixer because it is completely work as a passive mixer.
Next, we set a goal to design a power amplifier with 1-W saturation output power. We design two amplifiers in WIN GaN process, including Ku- and Ka- band PA. The Ka-band power amplifier suffer from heat issue and fail to work. That is the reason why we design Ku-band version PA. The Ku-band successfully work as a 15-dB gain and nearly 29-dBm saturation output power from 10 GHz to 15 GHz.
Finally, we try to design a W-band PA in 40 nm CMOS process. We set a goal to achieve the center operating frequency at 94 GHz. It is the parasitic issue that makes a W-band PA suffer from high loss in matching network and passive component in the circuit. As a result, we fail to make this PA work due to misestimation of in-band bypass capacitor EM simulation. In Chapter 4, we will present how to debug and make the PA work.
Overall, we have consulted block diagrams in front-end communication system except for TX/RX switch and antenna design. Besides, a low noise down converter haven been taped out. It would be measured and make a front-end communication closer to be complete. In the future, the whole system should be integrated with antenna by TX/RX switch. |
