鍺與砷化銦鎵鰭式場效電晶體共閘極製程之開發;Development of a Common Gate-Stack Process for Ge and InGaAs Fin Field-Effect Transistors

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题名:	鍺與砷化銦鎵鰭式場效電晶體共閘極製程之開發;Development of a Common Gate-Stack Process for Ge and InGaAs Fin Field-Effect Transistors
作者:	許乃蓉;Hsu, Nai-Rong
贡献者:	電機工程學系
关键词:	共閘極;鍺;砷化銦鎵;鰭式場效電晶體;Common gate;Ge;InGaAs;FinFET
日期:	2017-08-21
上传时间:	2017-10-27 16:14:35 (UTC+8)
出版者:	國立中央大學
摘要:	隨著積體電路技術的快速發展與進步，製程技術逐漸接近物理極限，需要找尋新的可行性且接受度大的通道材料來突破此困境，根據產業技術發展現況判斷，鍺的電洞遷移率為矽的數倍，所以被認為很可能是未來金氧半場效電晶體的P型通道材料，而N型通道材料則可能會由具有高電子遷移率的III-V族砷化物擔綱。然而，要實現異質整合之鍺與砷化銦鎵互補式金氧半電晶體，必須先解決目前高介電常數材料與半導體界面缺陷重多的問題。而兩者相較，又以鍺之閘極製程較為成熟與穩定，因此，本研究以鍺之閘極製程為基礎，提出一種新穎的半導體表面處理方法，可同時適用於奈米級鍺與砷化銦鎵鰭式場效電晶體之製作，以利鍺與砷化銦鎵互補式金氧半電晶體之整合。本研究是以原子層沉積法成長的氧化鋁作為高介電常數材料，首先以電容的特性來評估此製程之可行性，其製作方式為將鍺與砷化銦鎵磊晶片經化學溶液清潔、熱氧化處理以及電漿處理後，立即沉積氧化鋁於其上。所製作的氧化鋁/(鍺，砷化銦鎵)電容特性顯示，在室溫下的調變率分別為55%和72%，以電導法估計界面補陷密度，前者在價電帶附近的界面補陷密度為7.85×1011 eV-1cm-2，後者在導電帶附近的界面補陷密度約為2.58×1011 eV-1cm-2，顯示氮氣電漿處理可同時有效降低二者之界面捕陷。後續之實驗顯示，氮氣電漿處理亦可以提升元件之熱穩定性。氧化鋁/(鍺，砷化銦鎵)電容經550oC快速熱退火後，砷化銦鎵電容在累積區之頻散現象從3.4%/dec減小至2.5%/dec，鍺電容之調變從72%提升至83%而頻散現象也從1.47%/dec減少至0.94%/dec。這些結果證實此共閘極製程技術應用於鍺與砷化銦鎵金氧半電晶體之可行性。在確認上述共閘極製程參數之後，吾人即以此技術製作鍺與砷化銦鎵無接面(junctionless)鰭式場效電晶體。其中，鍺通道層材料是以低壓化學氣相沉積法成長於Silicon on Insulator (SOI)基板上；砷化銦鎵通道層材料則是以分子束磊晶法成長於以磷化銦基板之砷化銦鋁緩衝層上。鰭式場效電晶體是以電子束微影系統進行鰭式通道與閘極區域的定義，其中Ge pFinFET與InGaAs nFinFET之閘極長度與鰭通道寬度分別為 80 nm/30 nm與 40 nm/60 nm。以此閘極製程同時製作之鍺與砷化銦鎵鰭式場效電晶體均具有電晶體之調變特性，其開關電流比分別為104與103，最大汲極電流密度分別為60 µA/µm與2 µA/µm，次臨界擺幅分別為180 mV/dec與384 mV/dec，且其閘極漏電流均低於10-4 µA/µm。雖然砷化銦鎵鰭式場效電晶體之汲極電流密度因通道過度蝕刻而過小，此研究已初步顯示此共閘極製程在未來積體電路製造之應用潛力。;Following the rapid development of integrated circuit technology, the quest for integrating high-mobility channel metal-oxide-semiconductor field-effect transistors (MOSFETs) has become even more urgent because current aggressively scaled devices are approaching their physical limit. As indicated by the recent status of material technology, Ge, which has higher hole mobility than Si, is likely to be the choice for p-channel MOSFETs, while high electron mobility III-V materials, such as InGaAs, could be used for the n-channel MOSFETs. However, to realize the integrated Ge and InGaAs CMOS scheme, one has to cope with the complex structure and composition of the native oxides of Ge and InGaAs, which result in defect states at the oxide-semiconductor interface. Since the gate-stack process of Ge MOS, which involves rapid thermal oxidation (RTO), is a rather mature process, this work is devoted to the development of a common gate-stack process based on this process so that it can be used to fabricate Ge and InGaAs fin field effect transistors (FinFETs) simultaneously. In this study, Al2O3 prepared by atomic layer deposition (ALD) is used as a high dielectric constant material. The feasibility of this common gate-stack process is evaluated based on the characteristics of Ge and InGaAs metal-oxide-semiconductor capacitors (MOSCAPs). The Ge and InGaAs epilayers were chemically cleaned in an HF solution and subjected to a RTO process. Then, the samples were treated by nitrogen plasma right before the deposition of the Al2O3 gate dielectric. Post metal annealing (PMA) was performed to reduce the oxide traps and the border traps near the oxide-semiconductor interface. The Ge and InGaAs MOSCAPs prepared by the nitrogen plasma treatment show effective capacitance modulations of 55% and 72%, respectively. Their interface trap density is 7.85×1011 eV-1cm-2 near the valence band, and 2.58×1011 eV-1cm-2 near the conduction band, respectively, as extracted by the conductance method. It indicates that nitrogen plasma treatment can effectively decrease interface traps in both InGaAs and Ge MOSCAPs. A series heating experiments shows that nitrogen plasma treatment can also improve the thermal stability of MOSCAPs. After rapid thermal annealing at 550°C, the dispersion of CV curves in accumulation region decreases from 3.4%/dec to 2.5%/dec for the InGaAs MOSCAP and from 1.47%/dec to 0.94%/dec for the Ge MOSCAP. In addition, the Ge MOSCAP’s modulation improves from 72% to 83%. After confirming the common gate process parameters, the proposed gate-stack process was used to fabricate junctionless (Ge,InGaAs) FinFETs. The Ge channel layer material was grown on a silicon-on- insulator (SOI) substrate by low pressure chemical vapor deposition, and the InGaAs channel layer material was grown on an InP substrate with an InAlAs buffer layer by molecular beam epitaxy (MBE). The gate length (Lg) and fin width (Wfin) of the Ge pFinFET and InGaAs nFinFET prepared by electron beam exposure are 80 nm/30 nm and 40 nm/60 nm, respectively. The Ge and InGaAs FinFETs exhibit Ion/Ioff ratio of 104 and 103, subthreshold swing of 180 mV/de and 384 mV/dec, and maximum drain current of 60 µA/µm and 2 µA/µm, respectively. The gate leakage current for both the Ge and InGaAs FinFETs is below 10-4 µA/µm. Although the drain current density of the InGaAs FinFETs is unexpectedly small, which may be due to over etching, this work has demonstrated the feasibility of this common gate process for Ge/InGaAs CMOS integrated circuits.
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