閘極掘入式製程是製作增強型氮化鎵異質結構場效電晶體常用的一種方法，目前主要是以電漿乾蝕刻方式為之。為避免蝕刻深度不穩定之問題及減少電漿蝕刻傷害，本論文研究提出以氫氧化鉀濕蝕刻方式製作增強型氮化鋁銦/氮化鎵異質結構金氧半場效電晶體。此研究所使用的磊晶結構具有氮化鎵披覆層，利用氫氧化鉀對氮化鋁銦與氮化鎵的高選擇性蝕刻比，此氮化鎵披覆層能作為濕蝕刻保護層，而氮化鎵通道層也能扮演蝕刻停止層的角色，以期獲得晶圓均勻的臨界電壓。AFM結果顯示，利用氫氧化鉀濕蝕刻方式能有效控制蝕刻深度且蝕刻線寬無明顯橫向擴張。若定義導通電流達到1 mA/mm時之電壓值為臨界電壓，所製作之增強型Ni/SiO2/GaN MIS電晶體在濕蝕刻10分鐘與15分鐘後的臨界電壓分別為1.4 V與1.1 V；閘極漏電流可低至10-7 mA/mm；在Vg= 15 V下，最大導通電流為441 mA/mm；Ion/Ioff ratio為 107；崩潰電壓可達287 V；經過10 msec Vd= 200 V 截止偏壓，在開啟後2 msec所得之動態電阻比值為1.4。此外，閘極C-V遲滯量測結果顯示，濕蝕刻增強型元件遲滯量為1.06 V，相較於乾式蝕刻增強型元件之遲滯量1.66 V為低，表示此論文所提出之KOH濕蝕刻確實引發較少的界面補陷(trap)，惟後續仍須使用如原子層沉積法之製程製作MIS元件，以釐清閘極掘入製程與閘極介電層製程各自引發之界面補陷有多寡。;Gate-recess is a typical process to fabricate enhancement-mode GaN-based heterostructure field-effect transistors (HFETs). Due to the inertness of GaN-based materials, the gate-recess process is often carried out by plasma etching. To avoid the issues associated with etching depth control and plsma damage, a KOH wet-etching method is proposed and developed for the fabrication of AlInN/GaN metal-insulator-semiconductor (MIS) FETs in this study. Owing to the high etching rate selectivity of AlInN over GaN, the GaN channel layer itself can serve as an etch-stop layer, resulting in a uniform recess depth and Vth across the wafer. Atomic force microscopy images show that the use of the KOH wet-etching method can effectively control the etching depth and linewidth without significant lateral etch. Enhancement-mode devices are successfully fabricated with Vth values of 1.4 V and 1.1 V (Id = 1 mA/mm) for the KOH wet-etching time of 10 min and 15 min, respectively. The devices exhibit a maximum current density of 441 mA/mm at Vg= 15 V, an Ion/Ioff ratio of 107 with a gate leakage current as low as 10-7 mA/mm and an off-state breakage voltage of 287 V. Dynamic Ron ratio of 1.4 is also obtained after Vd off-state stress of 200 V for 10 ms. In addition, the hysteresis of gate C-V curves of the KOH etched device is 1.06 V, while that of the plasma-etched device is 1.66 V. This suggests that the KOH wet etching process leads to fewer interface traps. However, further study on the MIS interface is needed in order to clarify the effects of gate recess process and gate dielectric deposition process on the density of interfacial traps, respectively.
