積體電路隨著製程的精進與微縮，元件尺寸持續下探到物理極限，為我們帶來體積更小、效率更高的電子設備。但是隨之而來的卻是更艱難的製程要求和更嚴重的非理想效應，造成產品的良率下降，影響成本與品質。 電容是積體電路中重要的被動元件之一，在許多類比電路中，需要精確的電容值來實現正確的電路功能，隨著元件到達數奈米等級的製程，半導體設備運行中所遇到的隨機變動，對電容參數的影響更甚以往，若無採取適當的對策，甚至會造成電路失效。因此對於設計者而言，如何在設計階段就能評估電路抵抗製程變動能力，將是決定最後產品良率的關鍵。 本論文針對兩任意比例的電容陣列所遇到的隨機與系統性變動，推導出矩陣形式的分析法評估其對單位電容陣列的影響，並且得以加入多種系統變動與各種擺放形式做出交叉評估，最後採用matlab統計分析軟體來模擬各種情境下兩電容陣列的不匹配程度，並用實例來驗證和說明分析結果。 ;The integrated circuit has become more and more sophisticated, moreover, the feature size of device is shrunk to the physical limit. Smaller circuit brings the more efficient electronic product. However, the attendant problem on complex technology is strict quality and critical non-ideal effect of semiconductor that reduces the yield of product, quality and rises the cost. Capacitance is the one of the most important passive device in the circuit. In the analog circuit, the correct function is dominated by the accuracy value of capacitance. With the components to reach the number of nano-level process, the random mismatch of the equipment will acutely affect the parameter of capacitance during the step of process. Without an appropriate strategy, the mismatching device will fail the circuit if worse coming to worst. For the designer, how to evaluate the performance of circuit to tolerate the process variation at the step of layout is the key point of reliable chip. This thesis research the mismatch of two general-ratio block capacitance with random and systematic variation. We derive the matrix analysis for estimating the mismatch of two unit-capacitance arrays. Furthermore, we consider the common systematic variation and placement into the matrix analysis. Finally, we use the matlab and case to verify the result of mismatch with process variation.
