本篇論文研究內容是在IEEE 802.11ac所訂定之規格下，實現一寬頻低功耗發射機之整合型電路，其中包含兩顆晶片，第一顆晶片為單路同相(In-phase)之發射機，利用tsmcTM 90 nm CMOS製程來實現。基頻部分使用CMOS基頻反向式放大器以及電阻回授來使得輸出阻抗提升以及將偏壓簡單化；升頻混波器採用電流模態被動混頻器來達到低功耗以及高線性度的特性；功率放大器之驅動級使用疊接架構達到較高之轉換增益使得輸出功率能提高，以及使用電阻電容串聯回授改善穩定度，輸出端藉由設計一電感性耦合共振腔巴倫以達到寬頻功率匹配。量測時固定本地震盪功率為6 dBm進行量測，在中心頻率為8 GHz時轉換增益為14.38 dB，輸出功率1-dB壓縮點為 -0.75 dBm，輸出三階交互調變點為10.85 dBm，增益頻寬為5 - 10.5 GHz，本地震盪埠至射頻輸出埠之隔離度為21.99 dB，整體直流功耗64.81mW，晶片面積大小為1.21 × 0.818 mm2。 第二顆晶片為整合同相以及正交相(Quadrature-phase)二分之一周期之IQ寬頻發射機電路，利用tsmcTM 90 nm CMOS製程來實現，本地震盪端加入一電流模態邏輯之除頻器電路以產生四相位訊號，I路以及Q路訊號直接結合以達到電路簡單化。量測時固定本地震盪功率為14 dBm，晶片的直流打線到印刷電路板進行量測，在中心頻率為8 GHz時轉換增益為12.9 dB，輸出功率1-dB壓縮點為 -4.17 dBm，輸出之三階失真點為16.47 dBm，本地震盪埠之載波抑制為30.02 dBc，頻帶內之邊帶抑制為39.62 dBc，增益頻寬為5 - 10.5 GHz，整體直流功耗為66.36mW，晶片面積大小為1.245 × 1.099 mm2。 ;This thesis developed a fully integrated wideband and low power I/Q transmitter under the specifications of IEEE 802.11ac. There are two chips in the thesis. The first chip in chapter 2 is fabricated in tsmcTM 90 nm CMOS technology. The author applied a CMOS baseband inverter-type amplifier with resistive-feedback which increases the output impedance in the baseband circuit. The up-conversion mixer is adopted current-mode passive mixer for low power and high linearity application. The driver amplifier is used cascode topology which enhances the conversion gain to increase output power performance. For the stability condition, the resistor-capacitor (RC) feedback is applied in the driver amplifier. In the output of the amplifier, an inductively coupled resonator transformer-type balun is adopted for the wideband power matching. The proposed I-channel transmitter exhibits a measured conversion gain of 14.376 dB, an output 1-dB compression point of -0.75 dBm and an OIP3 of 10.854 dBm under the LO power of 6 dBm at the center frequency of 8 GHz. The measured gain bandwidth is 5 - 10.5 GHz and the LO-port to RF-port isolation is 21.99 dB. The chip consumes the dc power of 64.81 mW and occupies 1.21 × 0.818 mm2. The second chip is a wideband transmitter circuit which integrates in-phase and quadrature-phase 50% duty-cycle signal and fabricated in tsmcTM 90 nm CMOS technology. A current-mode logic divider in the LO-port is presented, which is used to generate I/Q signal. For simplicity, the up-conversion I/Q signal is direct-combining to solve the problem of the sideband interference. For the measurement conditions, the chip bias is bounded to print circuit board. The proposed I/Q transmitter exhibits the measured conversion gain of 12.9 dB, an output 1-dB compression point of -4.17 dBm, an OIP3 of 16.47 dBm, a carrier suppression of 30.02 dBc and a sideband suppression of 39.62 dBc under the LO power of 14 dBm at the center frequency of 8 GHz. The measured gain bandwidth is 5 - 10.5 GHz and the chip consumes a dc power of 66.362 mW and occupies an area of 1.245 × 1.099 mm2.
