由本論文研究之實驗結果顯示，所提出之非合金歐姆接觸金屬堆疊結構極適用於n型砷化銦鎵金氧半場效電晶體，未來將可應用於三五/矽異質整合積體電路之製造。;For the past five decades, the development of Si-based CMOS manufacturing technology has been following Moore′s Law in shrinking the physical dimension and enhancing the device performance of integrated circuits. As the manufacturing technology approaches its limit, potential solutions in terms of materials and processes are explored extensively in recent years. Among many novel materials, III-V compounds such as GaAs and InGaAs, which have high electron mobility, are considered very promising for n-channel field-effect transistors (FETs). For these arsenide-based materials, Au-based metal stack for ohmic contacts is fairly popular and mature. However, Au is a notorious contaminant in Si processes, and is strictly prohibited in a Si fab. In this work, an Au-free ohmic contact metal stack is proposed and verified on n-channel InGaAs MOSFETs.
The proposed ohimic metal stack on n-type InGaAs consists of Ti (titanium) and AlSiCu (aluminum silicon copper alloy). Transmission line method (transfer length method, TLM) measurements indicate that specific contact resistivity (ρc) as low as 2.85×10-7 Ω-cm2 without post-metal annealing has been achieved without any alloying process. Thermal stability and current stress tests also demonstrate the feasibility of this ohmic contact stack.
This ohmic metal stack is applied to both InGaAs junctionless planar MOSFETs and fin field-effect transistors (FinFETs). The channel width (Wch) and gate length (Lg) of n-InGaAs MOSFETs and FinFETs are 1.5 µm/0.7 µm and 80 nm/40 nm, respectively. The n-InGaAs MOSFETs and FinFETs exhibit an Ion/Ioff ratio of 104 and 102, a maximum drain current density of 216 µA/µm and 38 µA/µm, and a subthreshold swing (S.S.) of 180 mV/dec and 350 mV/dec, respectively. The gate leakage current density of n-InGaAs MOSFET and FinFET is below 1×10-3 µA/µm.
As indicated by the results above, the non-alloyed Au-free ohmic contact stack is very suitable for n-InGaAs MOSFETs, and should be applicable to III-V/Si heterogeneous integrated circuits in the future.
