砷化銦鎵/銻砷化鎵第二型異質接面P通道穿隧場效電晶體之設計與模擬;Design and Simulation of P-channel InGaAs/GaAsSb Staggered Hetero-Junction Tunneling Field-Effect Transistors

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/75956

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/75956

Title:	砷化銦鎵/銻砷化鎵第二型異質接面P通道穿隧場效電晶體之設計與模擬;Design and Simulation of P-channel InGaAs/GaAsSb Staggered Hetero-Junction Tunneling Field-Effect Transistors
Authors:	陳妗仰;Chen, Jin-Yang
Contributors:	電機工程學系
Keywords:	P型穿隧式場效電晶體;砷化銦鎵;銻砷化鎵;電腦輔助設計;pTFET;InGaAs;GaAsSb;TCAD
Date:	2018-01-29
Issue Date:	2018-04-13 11:24:31 (UTC+8)
Publisher:	國立中央大學
Abstract:	過去五十年，積體電路中的電晶體密度隨著摩爾定律持續增加，積體電路之功率消耗與功率密度也快速提升，所造成的熱效應已是未來積體電路發展的瓶頸之一。為解決此問題，最直接的方式便是降低元件操作電壓。但為了維持效能，電晶體之臨限電壓(threshold voltage)必須跟著低，同時次臨限擺幅與關閉電流也必須降低。傳統金氧半場效電晶體(MOSFETs)是以載子漂移-擴散的機制傳導，其次臨限擺幅(subthreshold swing)被限制在60 mV/decade 以上。若是改以穿隧機制作為電晶體之導電機制，其次臨限擺幅則可突破此限制，成為下一世代低耗能積體電路之選項。由於三五族材料中的砷化銦鎵/銻砷化鎵(InGaAs/GaAsSb)可行成第二型異質接面，特別適合穿隧式場效電晶體之用，透過不同成分組合可調整穿隧能障，優化元件電性。本研究即以此異質接面為基礎，設計P通道穿隧式場效電晶體，利用TCAD模擬軟體建立穿隧式場效電晶體物理模型，模擬不同成分砷化銦鎵/銻砷化鎵的能帶組合、摻雜濃度變化、閘極位置、氧化層和通道接面的缺陷，對元件特性的影響。根據模擬結果，選擇具有低關閉電流適合用於低功耗產品上，且與磷化銦(InP)基板晶格匹配的In0.53Ga0.47As/GaAs0.51Sb0.49組合持續優化。在元件特性優化上，於源極和通道接面加入一層銻化鎵材料，異質接面處的等效能障由0.63 eV 降到0.38 eV，在VDS = - 0.3 V，VGS = - 0.5 V時的汲極電流提高到24 μA/μm，關閉電流依然維持在4×10-11 μA/μm，用此方法來調整接面能障能有效提升元件特性。而加入多層過渡層後，在VDS = - 0.3 V，VGS = - 0.5 V 時的汲極電流將可再提高到34 μA/μm 同時兼顧低關閉電流。為了持續優化直流特性，改善元件開關速度，最後選擇In0.53Ga0.47As/GaAs0.51Sb0.49 組合的低關閉電流與InAs/GaAs0.1Sb0.9 組合的高導通電流這兩個優勢相互結合，成功地將導通電流提升達86 μA/μm，而臨限電壓可以降低到 - 40 mV，令元件可以更快導通。而為了降低多種材料上的磊晶成本，因此將通道與汲極替換成其他成分的GaAsSb，透過不同材料間的晶格不匹配關係來分別引入伸張(tensile) 和壓縮(compressive)應變效應，當壓縮應變達到2 %後，汲極電流增加到28 μA/μm，與單層插入層有相同效果，完成砷化銦鎵/銻砷化鎵第二型異質接面P 通道穿隧場效電晶體之設計與模擬。;With the progress of semiconductor science and technology, the number of metal-oxide-semiconductor field-effect transistors (MOSFETs) in integrated circuits continuely increases over the last 50 years following Moore’s Law. The rapidly increasing power consumption associated with transistor density becomes one of the major bottlenecks in the development of future integrated circuits. An intuitive approach to this problem is to lower the operation voltage and threshold voltage simultaneously. Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing (S.S.) is limited to 60 mV/decade or higher at room temperature. Whereas, tunneling field-effect transistors (TFETs) is considered as a promising candidate device for low voltage and low power integrated circuits, which is based on band-to-band tunneling (BTBT) to generate current that can break through the limit of S.S. (60 mV/decade). In III-V compound semiconductors, InGaAs/GaAsSb material system allows us to modulate band lineups by changing their compositions to form staggered type heterojunction TFETs. In this study, pTFETs based on this material system is investigated using Synopsys Sentaurus TCAD tool. The effects of band alignment, doping concentration, gate position and traps at III-V/oxide interface on the electrical properties of InGaAs/GaAsSb TFETs are systematically studied. Simulation results show that there is a strong correlation between tunneling barrier (Ebeff) with on/off-currents (ION and IOFF). Higher Ebeff leads to lower ION and IOFF, while the lower Ebeff results in higher ION and IOFF. To reach high ION and low IOFF, In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer is proposed to reduce Ebeff from 0.63 eV to 0.38 eV at the source/channel junction, which leads to an ION current equal to 24 μA/μm at VDS = - 0.3 V，VGS = - 0.5 V, while IOFF remains at 4×10-11 μA/μm at VGS = 0 V, simultaneously. To improve the device performance further and increase the switching speed, a low IOFF of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET combination with a high ION of InAs/GaAs0.1Sb0.9 insertion layer is proposed. Based on this design, ION can be further enhanced to 86 μA/μm and the threshold voltage can be reduced to - 40 mV. The effects of strain introduced by lattice mismatch between GaAsSb and In0.53Ga0.47As on the device performance are also studied. A 2 % compressive strain makes ION increase to 28 μA/μm, which is equal to the ION of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer, and its IOFF also remains at 10-11 μA/μm.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	264	View/Open

社群 sharing

Loading...