| 摘要: | 本篇論文提出一個94-GHz接收機前端電路，採用90-nm CMOS製程，電路架構為整合五級之低雜訊放大器、寬頻之LO巴倫、單平衡架構之混頻器與倍頻器，其可在輸出10 MHz 之IF 頻率下提供量測轉換增益33 dB 與雙邊頻帶雜訊14 dB，在偏壓1 V 情況下只有20.4 mW之功耗。
為了驗證接收機前端電路、改善電路特性以及系統的完整性，本論文第二章提出94-GHz可調增益接收機電路，是採用90-nm CMOS製程整合GIPD製程實現，利用GIPD製程具有高阻值的矽基板，以及其低損耗金屬走線的優勢，為了節省成本與提升被動元件的Q值，GIPD製程適用於微波與毫米波被動電路的設計，封裝整合必是未來趨勢，本設計會驗證整合的連接結構。而RF端屬於94-GHz的高頻訊號，經過400 μm的線長再到達實際電路裡面，中間必有損耗是我們需要校正掉的，所以在GIPD會做de-embedding的動作。此可調增益接收機包括低雜訊放大器、倍頻器、混頻器和可調增益中頻放大器，主要為延續前一章的架構。校正後其量測結果在90 GHz有最大轉換增益48 dB，增益可調範圍為40 dB，RF的3-dB 頻寬為6.5 GHz，約為7.2%，IF的3-dB 頻寬在最高與最低增益分別為1 GHz和1.7 GHz，P1dB在最高與最低增益分別為-43.5 dBm和-29 dBm，雜訊指數則為12.5 dB以下，在偏壓1 V和1.2 V的情況下有共約62 mW之功耗。
隨著無線通訊系統的資料傳輸速率愈來愈快，本論文將設計太赫茲高速資料傳輸，提出創新之系統架構及電路，太赫茲高速收發機之200-GHz前端接收機之電路設計，利用40-nm CMOS技術實現，此電路架構為兩路的天線接收訊號，進入低雜訊放大器後當作混頻器RF輸入端，和藉由兩路100-GHz壓控震盪器產生訊號，且透過PLL去進行鎖定機制，將訊號穩定於100-GHz，再將訊號倍頻後，當作混頻器LO輸入端，而混頻器輸出端將同相的電流匯集至下一级的轉阻放大器再經限制放大器後輸出，此電路從低雜訊放大器輸入端到轉阻放大器的輸出端模擬有電壓轉換增益32 dB，P1dB為-23 dBm，輸出IF的3-dB頻寬約為13.4 GHz。
;In this thesis, a 94-GHz receiver front-end (RFE) in 90 nm CMOS technology is presented. The RFE integrates a five-stage low-noise amplifier, a broadband LO balun, a single-balanced mixer, and a doubler. The measurement system provides voltage conversion gain of 33 dB and double-sideband noise figure of 14 dB at the IF frequency of 10 MHz while only consuming 20.4 mW from a 1 V supply.
To verify the receiver front-end circuitry, improve circuit characteristics and system integrity, in chapter two, a 94-GHz receiver variable-gain in 90 nm CMOS integrated IPD process is presented. The CMOS chip is flipped and bonded onto the carrier through the transition. The advantages of IPD process are silicon substrate of high resistivity and low-loss metal to cut down the cost and improve the quality factor (Q) of passive components. However, we must verify the transition and calibrate the RF input loss of trace from GIPD to 90-nm interconnects by consideration of TRL de-embedding. The RX system which continuation of the previous chapter of the design include a five-stage low-noise amplifier, a broadband LO balun, a single-balanced mixer and a variable-gain amplifier. The measurement system provides voltage conversion gain of 48 dB, tuning range 40 dB at 86 GHz~92 GHz, IF bandwidth achieves 1.7 GHz at low gain and 1 GHz at high gain, the range of P1dB is -43.5 dBm ~ -29 dBm and double-sideband noise figure of 12.5 dB at the IF frequency of 10 MHz while iv consuming 62 mW from a 1 V and 1.2 V supply.
Finally, because of the wireless communication system popularity and the higher data rate. The third part is the design of the 200-GHz receiver using 40-nm CMOS technology. This circuit consists of antennas, VCOs, PLLs, LNAs, doublers, triplers, mixers, a TIA and a LA. The design of receiver is divided into two way from LNA to mixer and combine the in-phase current at mixer load to next stage, TIA. The simulated voltage gain from LNAs to TIA provide 32 dB, P1dB is -23 dBm and the IF bandwidth can achieve 13.4 GHz. |
