基於自動調節機制分散式K最佳演算法之軟性輸出的多輸入多輸出偵測器設計與實現;Design and Implementation of Soft-output MIMO Detector Based on Self-adjusting Distributed K-Best Algorithm

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題名:	基於自動調節機制分散式K最佳演算法之軟性輸出的多輸入多輸出偵測器設計與實現;Design and Implementation of Soft-output MIMO Detector Based on Self-adjusting Distributed K-Best Algorithm
作者:	王偉丞;Wang, Wei-Cheng
貢獻者:	電機工程學系
關鍵詞:	多輸入多輸出系統;軟性輸出;MIMO;soft output
日期:	2018-07-20
上傳時間:	2018-08-31 14:50:31 (UTC+8)
出版者:	國立中央大學
摘要:	本論文著重在傳統分佈型K-最佳演算法為基礎的低複雜度K-最佳多輸入多輸出解碼器的效能改善，並加入位元對數相似比(Bit level Log Likelihood Ratio, LLR)利用軟性調解多輸入多輸出偵測器之位元錯誤率使效能提升，本解碼器結合了兩種可適性自動調節機制來達到比傳統分佈型K-最佳演算法還低的運算複雜度，分別為適應性連續消除機制(ADSIC)與適應性K值選取機制(ADK)。適應性連續消除機制(ADSIC)於每一層解碼訊號時計算出每一個母點的最佳子點，運用其相同性決定是否來執行連續消除機制演算法。另外適應性K值選取機制(ADK)，異於傳統適應性K值選取機制需要估測SNR大小來調整K值，在其中只需利用其PED差值來決定K值大小即可，整套完整的流程更利於在適應性K值選取機制上更有效率被使用。在硬體實現上，使用的是管線是架構來設計用來提高硬體操作頻率增加吞吐量，晶片實現方面是利用90nm製成來實現晶片設計，晶片的核心面積1.18mm×1.19mm，最高操作頻率167MHz且功率消耗為55mW。最後，本設計使用SMIMS VeriEnterprise Xilinx FPGA板驗證其電路功能，於下線前確保所設計電路功能正確。;This thesis focus on low complexity K-Best MIMO detector based on conventional distributed K-Best (DKB) and improving this performance by using bit level log likelihood ratio (LLR) to induce bit error rate. The algorithm combines two self-adjusting mechanisms which are adaptive successive interference cancellation (ADSIC) and adaptive K value chooser (ADK). The principle of ADSIC is to determine the execution of SIC based on similarity of First-Child. The First-Child can be found first by calculating every root’s signal in each layer. then identify the one that has least PED. After contrasting the one with each other, make the decision to execute SIC by the statistic of the same cases. On the other hands, ADK, the goal of the principle is that choose an appropriate K value at each layer by non-SNR measurement. Use the algorithm simulation to decision the appropriate threshold value and estimating the order of noise by smallest PED and second smallest PED. In this thesis, we use pipeline architecture to realize the propose MIMO detector with soft-output. It’s able to high clock rate and throughput. Finally, this design is implemented in 90 nm CMOS technology. The core area is 1.18mm×1.19mm. With supply voltage of 1V, the power consumption is 55mW and the maximum clock rate is 167MHz.
顯示於類別:	[電機工程研究所] 博碩士論文

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