使用注入鎖定技術之W頻段除三除頻器與V頻段除六除頻器及Q頻段鎖頻迴路;W-band Divide-by-3 Frequency Divider and V-band Divide-by-6 Frequency Divider and Q-band Frequency-Locked Loop Using Injection-Locked Technique

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題名:	使用注入鎖定技術之W頻段除三除頻器與V頻段除六除頻器及Q頻段鎖頻迴路;W-band Divide-by-3 Frequency Divider and V-band Divide-by-6 Frequency Divider and Q-band Frequency-Locked Loop Using Injection-Locked Technique
作者:	葉瀚濃;Han-Nung, Yeh
貢獻者:	電機工程學系
關鍵詞:	鎖頻迴路;注入鎖定;毫米波電路
日期:	2018-07-23
上傳時間:	2018-08-31 14:51:34 (UTC+8)
出版者:	國立中央大學
摘要:	主被動毫米波收發機應用於目標偵測是未來發展的趨勢，近年來半導體製程技術發展成熟，使用矽基製程來開發毫米波上的應用也得到新的進展。本論文主要針對毫米波注入鎖定技術應用於除頻器及鎖頻迴路，以達到低功耗、低相位雜訊之研究。第二章闡述一個W頻段高除數、高鎖定範圍使用電感匹配注入鎖定除頻器之分析、設計以及量測結果。第三章為V頻段注入鎖定除六頻器。最後，第四章為具鎖頻迴路自對準之次諧波注入鎖定振盪器之電路設計與量測結果。V頻段注入鎖定除六頻器及具鎖頻迴路自對準之次諧波注入鎖定振盪器採用台積電提供的90 nm互補式金氧半場效電晶體製程(TSMC 90 nm GUTM CMOS)。W頻段注入鎖定除三頻器則是採用台積電提供的40 nm互補式金氧半場效電晶體製程(TSMC 40 nm CMOS)。第二章將介紹除頻器架構與注入鎖定原理，並提出電感匹配注入鎖定三除頻器電路分析模型，理論結果與實驗結果相互驗證，並且使用台積電40 nm CMOS製程設計實現W頻段使用電感匹配注入鎖定除三除頻器，量測鎖定頻寬為10.1 GHz相當於10.2 %比例頻寬，電路直流總功耗為7.2 mW。第三章為V頻段注入鎖定除六除頻器的設計及分析，分析步驟大致與第二章分析除三除頻器相同，推導出鎖定頻寬公式，並且使用台積電90 nm GUTM CMOS製程設計實現一個V頻段注入鎖定除六除頻器，量測鎖定頻寬為5.6 GHz相當於9.8 %比例頻寬，電路直流總功耗為5.6 mW。第四章為具鎖頻迴路自對準之次諧波注入鎖定振盪器。首先介紹理論模型及轉移函數，接著利用ADS(advance design system)軟體進行模擬分析鎖頻迴路，能夠有效率的分析鎖頻迴路系統的開迴路及閉迴路響應。此外，利用提出的理論模型分析比較各種結構頻率合成器之相位雜訊及抖動量。量測的鎖頻範圍為33.4 到35.2 GHz，各個控制電壓的鎖定範圍約為50 MHz，輸出功率大於-7 dBm。當輸出鎖定頻率為33.9 GHz時，距載波偏移1 MHz的相位雜訊為-108.9 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz為144 fs。電路直流總功耗為70.6 mW。 ;The use of active and passive millimeter-wave transceivers for detection is a trend. In recent years, semiconductor process technology has matured, and the development of millimeter-wave applications using Silicon processes has also seen new advances. This thesis focuses on the application of millimeter wave injection locking technology in frequency divider and frequency locked loop to achieve low power consumption and low phase noise.Analysis, design and measured results for W-band high-division-ratio divide-by-3 injection-locked frequency divider (ILFD) in Chapter 2. Analysis, design and measured results of a V-band divide-by-6 ILFD are proposed in Chapter 3. Finally, the sub-harmonic injection-locked VCO with FLL self-alignment (SILFLL) are presented in Chapter 4. The V-band divide-by-6 ILFD and SILFLL in this thesis are fabricated using TSMC 90 nm GUTM CMOS process. The W-band ILFD is fabricated using TSMC 40 nm CMOS process. First, frequency dividers and the injection-locked theory are introduced in Chapter 2. Then, the locking range of divide-by-3 is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectors and the amplitude of the injection signal. Using inductor matching improves the locking range of divide-by-3. The proposed W-band divide-by-3 ILFD features a locking range of 10.1 GHz and a 10.2% fractional bandwidth. The power consumption is about 7.2 mW. In Chapter 3, we proposed a V-band divide-by-6 ILFD with low power consumption. The locking range is proportional to the device size of the injectors and the amplitude of the injection signal like in Chapter 2. The free-running oscillation frequency of the proposed ILFD is about 9.5 GHz and phase noise is -67.3 dBc/Hz. The measured locking range is about 5.6 GHz from 54.5 to 60.1 GHz with an input power -5 dBm. When the input signal is 144 GHz, the measured input and output phase noises at 100 kHz offset are respectively -125 and -140 dBc/Hz. The phase noise difference between input and output is about 15 dB, and it agrees with the theoretical calculation (20log6). The core power consumption is about 5.6 mW. A sub-harmonic injection-locked oscillator with frequency-locked loop self-alignment (SILFLL) are presented in Chapter 4. First, the theoretical models and transfer functions of FLL are introduced, then using ADS (advance design system) software with system setup analyses FLL. We can efficiently analyze the opened-loop and closed-loop responses of the FLL system. Furthermore, a theoretical model of the SILFLL is proposed, and used to calculate phase noise and jitter for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 33.4 to 35.2 GHz and locking range for each control voltage is about 50 MHz. The measured output power is higher than -7 dBm over the range. When the injection-locked output frequency is 33.9 GHz, the measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -108.9 dBc/Hz and 144 fs, respectively. The total power consumption is about 70.6 mW.
顯示於類別:	[電機工程研究所] 博碩士論文

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