利用笛卡爾偵測線及R樹保留繞線行為之類比佈局遷移技術;Analog Layout Migration Considering Routing Preservation with CDL-based R-tree

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Title:	利用笛卡爾偵測線及R樹保留繞線行為之類比佈局遷移技術;Analog Layout Migration Considering Routing Preservation with CDL-based R-tree
Authors:	洪嘉壕;Hung, Chia-Hao
Contributors:	電機工程學系
Keywords:	類比電路佈局;繞線保留;佈局遷移;R-樹;analog layout;layout migration;R-tree;routing preservation
Date:	2018-07-26
Issue Date:	2018-08-31 14:53:26 (UTC+8)
Publisher:	國立中央大學
Abstract:	由於製程演進的速度非常快，常常需要將舊製程的電路遷移到先進製程中，為降低非理想效應對電路效能的影響。重複使用已經設計好的佈局擺置和繞線，可以大大減少設計的時間。因此，佈局遷移自動化的目標，就是希望能完整記錄原始佈局的資訊，並在先進製程環境中重建佈局。這部分的相關研究已經很完整，但大多只記錄佈局擺置的資訊，有記錄佈局繞線行為的相關文章並不多，因為缺少原本繞線的行為，最後只能選擇最短路徑做佈局繞線，使電路中的寄生效應變成不匹配，而影響電路整體的效能。本論文提出一個在佈局遷移中記錄繞線行為的類比設計自動化流程，並提出一個快速紀錄繞線行為的方式–笛卡爾偵測線(CDL)，希望在佈局遷移中完整且快速的將繞線行為記錄下來，使佈局繞線不匹配的程度降到最低。在之前的研究中所採用的記錄方式，更新製程後可能會失去部分的記錄資訊，使得佈局繞線完整度不如預期，而我們提出的笛卡爾偵測線可以提高重建佈局繞線的完整度，完整重現每一條繞線的走向；另外，我們引入了一個快速區域搜尋的演算法R樹(R-tree)，有效提高了記錄佈局繞線的速度與準確度，如實驗數據所示，將電路從180nm遷移到90nm製程之後，此方法仍可完整保留繞線方式及電路效能。 ;Because of the fast evolution of VLSI process, migrating the old layout designs to advance technology is in need. In order to reduce the impact of non-ideal effects on circuit performance, reusing the placement and routing of well-designed layout is able to greatly reduce design time. Recording the design information of source layout completely and reconstructing the target layout in advance technology is often called as automatic layout migration. Most of previous research focus on placement preservation only without the discussion on preserving routing behavior. If the routing behavior of source layout is not considered, the shortest path result is often chosen as the routing for target layout, which may induce extra mismatching effects and change circuit performance. This thesis proposes a routing behavior preservation approach for analog layout migration. Based on the proposed Cartesian Detection Line(CDL), the routing behavior of original layouts can be preserved completely to used be reconstructed in new technology efficiently to reduce the routing mismatching. In previous works, the routing completeness may not reach 100%, because some routing information might be lost in new technology. Using the proposed CDL, the routing path of each net can be reconstructed completely to improve the routing completeness in new technology. In addition, a fast layout query algorithm based on R-tree is also proposed to enhance the speed and accuracy of routing reconstructing. As shown in the experimental results, the proposed algorithm successfully preserve the routing behavior and keep circuit in a good performance while migrating the circuit from 180nm process to 90nm process.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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