隨著製程進步，目前的超大型積體電路設計愈來愈複雜，單晶片系統( System on Chip , SOC ) 逐漸成為設計主流，由於系統通常同時包含數位電路與類比電路，因此類比/混合訊號(Analog/mixed-signal, AMS)電路的驗證在開發晶片的流程中變的格外重要。在這篇論文中，我們採用波動數位濾波器(Wave Digital Filter, WDF)，將類比電路轉換至對應的數位電路來進行仿真。此方法使用入射波與反射波的方式描述電路特性，可以將每個類比元件對應至波動數位濾波器架構的數位元件，達成與數位電路一起模擬的目標。 本研究根據WDF架構仿真流程之相關文獻，利用小訊號模型將三端的非線性元件拆解成數個雙端元件，本論文以查表的方式替換主動元件中非線性之效應，發現將切割表格的刻度縮小後會增加許多表格的容量。且為了在精準度及硬體成本之間權衡，必須對表格進行數學上的縮減。由實驗結果得知，在節省後的表格與原先表格的比較中，縮減的硬體最少可達99.97%。本研究也修改先前文獻的硬體架構，不需要在FPGA中軟體與硬體間的溝通。利用這兩點的改善；在硬體表現上，可達到20倍的加速，FPGA硬體的使用量與先前的研究也降低90%，由此可看出縮減表格對於波動數位濾波器的硬體仿真上的成效。 ;With the advance of process technologies, the design of Very-Large-Scale Integration (VLSI) circuits is becoming more complex. System on Chip (SOC) has become one possible option of VLSI design. Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter theory to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into corresponding digital component in WDF framework to support the co-simulation with digital circuits. Based on the relevant research of WDF emulation process, this thesis utilizes the small signal model of three-terminal MOSFET, hybrid-pi model, to decompose it to several two-port elements. We use lookup table to replace the non-linear effect in active element, and discover that decrease the scale of table will increase the table size massively. Owing to compromise the accuracy and hardware cost of table, we have to reduce the capacity of table. From the experimental results, the capacity of table can be reduced by 99.97% after table reduction. In this thesis, we also modify the hardware architecture of previous literature, and does not require communication between the software and the hardware in FPGA. Take the advantage of these two improvements, we can have 20 times faster acceleration in hardware performance. Comparing to previous work, FPGA hardware usage is also reduced by 90%. It demonstrates that table reduction technique is very effective in implementating hardware emulation of the WDF.
