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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/77732


    Title: 應用變壓器耦合與負偏壓技術於Ka頻段單刀雙擲開關器暨應用電容共振技術於X/Ka頻段III-V族開關器之研製;Implementations on Ka-band Single Pole Double Throw Switches with Transformer-coupled and Negative Bias Techniques and X/Ka-band III-V Switches with Resonant Capacitance Technique
    Authors: 傅奕文;Fu, Yi Wun
    Contributors: 電機工程學系
    Keywords: 單刀雙擲切換器;基底偏壓;Ka頻段;氮化砷;氮化鎵;互補式金氧半導體;SPDT;body bias;Ka band;GaAs;GaN;CMOS
    Date: 2018-07-30
    Issue Date: 2018-08-31 14:54:21 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文主要分兩部份,第一部份為應用於X頻段海事軍用雷達之單刀單擲切換器與單刀雙擲切換器,第一顆利用穩懋0.1 μm GaAs製程製作之單刀單擲切換器,採用並聯兩級切換器方式提升其隔離度,並利用串聯兩顆電晶體提升其1- dB功率壓縮點以符合海事雷達高功率需求,第二顆採用穩懋0.25 μm GaN製程設計單刀雙擲切換器,以等效四分之一波長有效降低晶片面積。
    第二部份為應用於Ka頻段主被動毫米波收發機之單刀雙擲切換器,第一顆晶片採用穩懋0.1 μm GaAs製程設計單刀雙擲切換器,使用電容共振技術將連接於電晶體之傳輸線寄生電感共振掉,使其擁有良好之隔離度,並利用並聯之傳輸線與電晶體共振於Ka頻段使其有擁有良好之特性並給予電晶體之汲極端直流準位,第二顆晶片為第一顆晶片之改善電路,分別於兩級切換器之第二顆電晶體並聯一傳輸線,利用其等效電感,共振其電晶體,使其擁有比上一顆晶片更好之隔離度與插入損耗。
    第三顆晶片為使用tsmcTM CMOS 90 nm 1P9M製程之單刀雙擲切換器,利用共振腔耦合之變壓器電路設計減緩隔離度與插入損耗之間的取捨,相較於傳統之行進波切換器有著更好的特性表現,再使用基底負偏壓技術減少寄生電容以改善插入損耗,並提升其1- dB功率壓縮點,最後使用閘極負偏壓技術,藉由臨界電壓與崩潰電壓找尋最適合之閘極偏壓,使功率承受能力能夠更進一步提升。
    ;Recent years have witnessed active research in the development of RF and millimeter wave wireless system. The switch is a critical component for various functions, such as radar, transmitter-receiver (Tx/Rx) duplexing in a time-division-duplexing (TDD) system. To obtain a high performance switch, the choice of the process is a very important factor. For example, high-speed electron mobility and high breakdown voltage are the advantages of Ⅲ-Ⅴ process, and it is suitable for marine radar and marine navigation. However, it is hard to integrate to single chip and its chip size is big. In contrast, CMOS process has the superiorities of low cost, and easy integration. But its major drawback is having low breakdown voltage. We need to choose the suitable process to approach the specifications of the circuit. To support the research plan of the laboratory, we use GaN、GaAs and the CMOS processes to implement X band and Ka band switches.
    The first work in Chapter 2 is fabricated in WINTM 0.1 μm GaAs technology. The author shunts two-stage switch to improve the isolation, and series two transistors to enhance the power handling. The simulated insertion loss of the proposed X band SPST is less than 0.8 dB, the isolation is better than 25 dB, and the IP1dB is 33 dBm.
    The second work in Chapter 3 is fabricated in WINTM 0.25 μm GaN technology. The author used the equivalent quarter wavelength transmission line to reduce the chip size. The simulated insertion loss of the proposed X band SPDT is less than 1.97 dB, the isolation is better than 37 dB, and the IP1dB at 10 GHz is 47 dBm.
    The third work in Chapter 4 is fabricated in WINTM 0.1 μm GaAs technology. The author used the resonant capacitance technique to resonate out the parasitic inductor of the transmission line to improve the isolation, and used distributed inductor to resonate out the parasitic capacitor of the MOSFET to improve the insertion loss. The simulated insertion loss of the first proposed Ka band SPDT is less than 1.8 dB, the isolation is better than 30 dB, and the IP1dB at 39 GHz is 35 dBm. The insertion loss of the second Ka band SPDT is less than 1.7 dB, and the isolation is better than 30 dB, and the IP1dB at 39 GHz is 32 dBm.
    The forth work in Chapter 5 is fabricated in tsmcTM 90 nm CMOS technology. The author used the transformer -coupled and negative bias to improve the insertion loss and isolation without trade off both specifications. The simulated insertion loss of the proposed Ka band SPDT is less than 1.9 dB, the isolation is better than 40 dB, and the IP1dB at 35 GHz is 25 dBm.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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