晶圓圖群集參數矽智財之設計;The Soft-IP Design of Cluster Number in Wafer Map Analysis

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/81392

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/81392

題名:	晶圓圖群集參數矽智財之設計;The Soft-IP Design of Cluster Number in Wafer Map Analysis
作者:	許家齊;Hsu, Chia-Chi
貢獻者:	電機工程學系
關鍵詞:	矽智財;晶圓圖;線性同餘法;線性反饋移位暫存器;Soft-IP;Wafer map;Linear congruential generator;Linear feedback shift register
日期:	2019-07-11
上傳時間:	2019-09-03 15:50:52 (UTC+8)
出版者:	國立中央大學
摘要:	在過去的晶圓群集參數NBD(瑕疵晶粒總數)、NCL(瑕疵晶粒連續線總數)的搜尋方式以及隨機撒點都是藉由軟體(MATLAB)的方式來進行分析及模擬，而本篇論文在探討晶圓群集參數的搜尋方式和隨機撒點都能夠改由硬體的方式來實現。而在硬體上要產生偽隨機數，主流的方式可以分為線性同餘法(Linear Congruential Generator)以及線性反饋移位暫存器(Linear feedback shift register) ，本篇論文是使用線性反饋移位暫存器(Linear feedback shift register)來進行隨機撒點其優點是架構簡單且容易實現，最重要的是速度相較於線性同餘法(Linear Congruential Generator)來得快。此外，由TSMC所提供之WM-811K晶圓圖，裡面的晶圓種類超過上千種,不同的晶圓尺寸需要不同的資料輸入量，這會導致需要編寫多個不同大小的晶圓群集參數搜尋電路，在本篇論文中，實現了Soft-IP能夠彈性地產生各種不同大小的晶圓群集參數搜尋電路，使用者只需透過參數的設定，就可以使得此晶圓群集參數搜尋電路彈性地對應各種不同大小的晶圓。最後，本篇論文所實現的電路架構是採用TSMC 0.18μm透過Synopsys Design Compiler合成，由實驗結果顯示，此電路的執行時間以及面積會隨著晶圓大小呈線性遞增。再來，為了驗證此Soft-IP實體化的可行性，我們將WM-811K裡面使用數量最多的晶圓W533透過Cadence Innovus進行Automatic Placement and Routing後，其電路可在14ns(71.42MHz)下運作。 ;In the past, the cluster number of wafer NBD (Number of Bad Die) and NCL (Number of Contiguous Line) and the random sprinkling defect were analyzed and simulated by software (MATLAB). In the paper, the search method of cluster number and random sprinkling defect of wafer can be realized by hardware. In the case of generating pseudo-random numbers on hardware, the mainstream method can be divided into Linear Congruential Generator and Linear Feedback Shift Register. This paper uses linear feedback shift register. The advantage of the linear feedback shift register for random sprinkling is that the architecture is simple and easy to implement. The most important thing is that the speed is faster than linear congruential generator. In addition, the WM-811K wafer map provided by TSMC has more than one thousand kinds of wafers. Different wafer sizes require different data input which will result in the need to write multiple different sizes of searching cluster number in wafer map circuits. In this paper, Soft-IP can flexibly generate searching cluster number in wafer map circuits of various sizes. Users can flexibly adapt the searching cluster number of wafer map circuits to various parameters through parameter setting. The size of the wafer. Finally, the proposed circuit architecture is synthesized by Synopsys Design Compiler using TSMC 0.18μm. The experimental results show that the execution time and area of this circuit will increase linearly with the wafer size. Then, in order to verify the feasibility of this soft-IP materialization, I used the most used wafer-W533 in WM-811K to Automatic Placement and Routing through Cadence Innovus, and the circuit can operate at 14ns(71.42MHz)
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
index.html		0Kb	HTML	158	檢視/開啟

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....