| 摘要: | 相位陣列常用於雷達系統中，用於調整波束的方向；在即將佈建的第五代行動通訊系統中，相位陣列也將扮演重要的角色。在相位陣列中，相位偏移器是最關鍵的電路元件之一，其功能為提供可調的相移量。在本論文中，我們提出兩種數位式相位偏移器，分別為使用磁耦合全通網路架構的被動式相移器及利用面積縮放技巧於向量疊加式架構的主動式偏移器，並以積體電路形式實現，操作於S頻段。
全通網路過去曾用於相移器設計中。具磁耦合的全通網路，若其耦合的極性為正，可用於提升相移器的相移量。在本論文中的第二章中，我們採用耦合係數為正的磁耦合全通網路架構，設計一2.45-GHz 五位元被動式相移器，目標為一級網路即可達到180°的相移量。我們使用 TSMC 0.18-μm CMOS製程來實現相移器中的可切換式電容，並搭配一積體被動元件（IPD）製程來實現耦合電感於矽載板上，最後以覆晶鍵合技術來接合CMOS晶片與IPD載板，完成此相移器。量測結果顯示，若可切換式電容按原設計方式控制，於2.45-GHz下相移量可達179.4°，然而並非全部32種狀態下的返回損耗皆可大於10 dB。若適當調整各別可切換式電容的控制狀態，最後調整為23種狀態組合，則於2 GHz下，返回損耗皆大於 10 dB，植入損耗皆小於 14.5 dB，相移量可達 147.8°。
主動式相位偏移器常採用向量疊加式架構。在本論文的第三章中，我們使用TSMC 0.18-μm CMOS 製程來實現一3.5-GHz六位元向量疊加式主動式相移器，並採用面積縮放技巧於其可變增益放大器之設計。使用面積縮放技巧的優點在於相位誤差及振幅誤差可以藉增加可變增益放大器的控制位元數來不斷減少。量測結果顯示，在3.3–3.8 GHz間，均方根相位誤差小於 1.15°，振幅誤差在±0.45 dB 以內；於全部64種狀態下，輸入返回損耗皆大於 15 dB，輸入返回損耗皆大於 7.9 dB，增益皆大於−8.81 dB。量測均方根相位誤差小於 2°的頻率範圍為2.46–4.68 GHz。
向量疊加式相移器必須有正交訊號產生網路，常用的架構有R-C多相位濾波器及正交全通濾波器。在本論文的第四章，我們提出具磁耦合的正交全通濾波器，用於縮小晶片面積。我們使用砷化鎵積體被動元件製程來實現 1.8–2.2 GHz 正交全通濾波器。量測結果顯示，在電路性能差異不大的情況下，磁耦合正交全通濾波器的晶片面積為 0.101 mm2，而傳統正交全通濾波器晶片面積為0.154 mm2，換算下來有34%的縮減。
在本論文中，我們成功實現了S頻段被動與主動數位式相位偏移器晶片，並提出磁耦合正交全通濾波器。其中，運用面積縮放技巧的向量疊加式相移器擁有具競爭力的低相位及振幅誤差。此外，我們也驗證了磁耦合正交全通濾波器可大幅減少晶片面積。
;Phased array is commonly used in radar systems for beam steering. In 5th generation mobile communication system that will be deployed soon, phased array also plays an important role. Phase shifter, used for providing tunable phase shift, is one of the essential circuit components in phase arrays. In this thesis, two types of phase shifters, which are passive phase shifter based on magnetically coupled all-pass networks and vector-summing active phase shifter using area-resizing technique, are proposed. The phase shifters are realized in integrated circuit form and operate in S-band.
All-pass networks have been used in phase-shifter design. Magnetically coupled all-pass network (MCAPN) with positive coupling coefficient may be used to increase the amount of phase shift. In Chapter 2 of this thesis, a 2.45-GHz 5-bit passive phase shifter is designed based on MCAPN with positive coupling coefficient. The design goal is to achieve 180° phase shift with only one stage of network. The switched capacitors in the phase shifter are implemented using TSMC 0.18-μm CMOS technology. The coupled inductors are realized on a silicon carrier substrate using an integrated passive device (IPD) process. Finally, the phase shifter is completed by assembling the CMOS chip and IPD carrier substrate with flip-chip bonding. Measurement results show that, if the switched capacitors are controlled in the originally intended way, the phase shifter exhibits 179.4° phase shift at 2.45 GHz but the return loss is however not greater than 10 dB for all 32 states. If the controlling bits for individual switched capacitors are properly modified, ending up in 23 sets of states, then at 2 GHz, the return loss is greater than 10 dB and the insertion loss is less than 14.5 dB for these 23 sets of states. The phase shift achieved is 147.8° at 2 GHz.
Vector-summing architecture is usually adopted for the design of active phase shifters. In Chapter 3 of this thesis, a 3.5-GHz 6-bit vector-summing active phase shifter is designed in TSMC 0.18-μm CMOS. In addition, area-resizing technique is adopted for the design of the variable gain amplifiers (VGAs) in the vector-summing phase shifter. The advantage of the area-resizing technique is that the phase and amplitude errors may be indefinitely reduced by increasing the number of the controlling bits of the VGAs. Measurement results show that, from 3.3 to 3.8 GHz, the rms phase error is less than 1.15° and the amplitude error is within ±0.45 dB. For all 64 states, the input return loss is greater than 15 dB, the output return loss is greater than 7.9 dB, and the gain is greater than −8.81 dB. Moreover, between 2.46 and 4.68 GHz, the rms phase error is less than 2°.
Quadrature generation network is a necessity in vector-summing phase shifter. Common quadrature generation networks include R-C poly-phase filter and quadrature all-pass filter (QAF). In Chapter 4 of this thesis, QAF with magnetic coupling is proposed for reducing the chip area. 1.8–2.2 GHz QAFs are implemented using a GaAs-based IPD process. Measurement results show that, given that the circuit performances are similar, the magnetically coupled QAF (MCQAF) occupies a chip area of 0.101 mm2 whereas conventional QAF occupies 0.154 mm2. This translates into a 34% reduction in chip area.
In this work, S-band passive and active digital phase shifter chips are successfully realized and MCQAF is proposed. Among them, the vector-summing phase shifter that adopts area-resizing technique exhibits competitively low phase and amplitude errors. Besides, it is also demonstrated that the proposed MCQAF could considerably save chip area. |
