實現高效能的Brick Cell陣列乘法器;Implementation of High-Performance Brick Cell Array of Array Multiplier

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81467

Title:	實現高效能的Brick Cell陣列乘法器;Implementation of High-Performance Brick Cell Array of Array Multiplier
Authors:	許倫彰;Hsu, Lun-Chang
Contributors:	電機工程學系
Keywords:	Brick Cell;陣列乘法器;乘法器;Brick Cell;Array of Array Multiplier;Multiplier
Date:	2019-07-30
Issue Date:	2019-09-03 15:56:26 (UTC+8)
Publisher:	國立中央大學
Abstract:	常見的傳統乘法器大多經由PPA (Partial Product Array，部分乘積陣列)以增加其效能。本篇論文，我們實現一個高效能且基於陣列的架構，Brick Cell Array of Array (BC-AoA)。BC-AoA乘法器直接處理(N/2)^2個兩位元的Brick Cell，以避免PPA(部分乘積陣列)的產生，並且將錯位的Brick Cell垂直相加，其中N是乘數與被乘數的長度。它具有優異的效能和更緊湊的結構。我們將BC-AoA與同樣基於陣列架構的Vedic 和LUK乘法器做比較。在本論文中，我們實現一個新的乘法器架構，BC-AoA。並使用台灣半導體研究中心(Taiwan Semiconductor Research Institute, TSRI)提供的台灣積體電路製造股份有限公司(Taiwan Semiconductor Manufacturing Company Limited, TSMC) 90nm製程進行模擬BC-AoA和其他乘法器。;Most conventional multipliers deal with partial product array (PPA) via compression technique that improves the performance of multiplication. In this thesis, we implement a high-performance array of array-based structure, i.e., brick-cell array of array (BC-AoA). The proposed BC-AoA multiplier directly deals with (N/2)^2 two-bit brick cells, which prevents the production of the PPA and vertically adds the twisted brick cells and sums together, where N is the multiplier and multiplicand length. It exhibits excellent performance with a more compact structure. We compare BC-AoA with Vedic and LUK multiplier, which are both array of array-based structures. In this thesis, we implement a new structure of multiplier, BC-AoA. We simulate BC-AoA and another multipliers using the Taiwan Semiconductor Manufacturing Company Limited (TSMC) 90nm processes which provided by the Taiwan Semiconductor Research Institute (TSRI).
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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