在先進製程的技術中，在電路佈局時必須考慮愈來愈多的非理想效應。由於電路在佈局後模擬(Post-layout simulation)後性能經常大幅地下降，因此傳統類比電路自動化設計工具仍無法被設計者所接受。然而，佈局遷移(Layout migration)是一種比較可行的方法，根據原始電路佈局的拓樸，給定不同的電晶體尺寸或是不同的製程產生新的佈局，該技術不但可以大大減少設計的時間，也可以保留設 計者對類比電路的佈局經驗。 本論文提出一個類比電路佈局遷移的設計自動化流程，目的是將原始佈局的拓撲和設計條件遷移到目標佈局以改善電路性能。對於擺置和繞線遷移的演算法，在之前研究裡所採用的紀錄方式仍有進步的空間，因此在本論文中，使用深度優先 SP 演算法(Depth-First-Search-Sequence pair)記錄原始佈局所有可能的擺置關係，再利用笛卡爾偵測線(Cartesian Detection Line)快速且完整地記錄繞線行為，如同實驗結果所示，將電路從 90nm 遷移到 65nm 製程後，該佈局遷移流程不但可以完整保留佈局的方式和保持良好電路效能，相較之前的電路遷移方式也快速了許多。;In modern technology, more and more non-ideal effects should be considered in the circuit layout. Tool-generated analog layouts are still not well accepted by designers since notable performance loss often exists in post-layout simulations. Layout migration is one approach to generate a new layout for given circuits with different device sizes or different technology according to the original layout topology. This technology not only reduces the design time obviously but also preserves the valuable design expertise of designers. In this thesis, an automatic analog layout migration flow is proposed. The purpose is to migrate the design constraints and topology of the original layout to the target layout to enhance the circuit performance after layout. In previous work, the placement area and routing completion still have some space to be improved. Therefore, in this thesis, the possible placement of the original layout are recorded by using Depth-First Search-Sequence pair. Routing behavior of original layout are preserved completely with Cartesian Detection Line (CDL). As shown in the experimental results, the proposed algorithm keeps the circuits in a good performance and reduces the design time while migrating the circuits from 90nm to 65nm.
