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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81502


    Title: 具四階脈波振幅調變資料相位偵測器與還原資料選擇電路之10 Gb/s時脈與資料回復電路;A 10 Gb/s Clock and Data Recovery with PAM-4 Data Phase Detection and Recovered Data Selection
    Authors: 林修華;Lin, Hsiu-Hua
    Contributors: 電機工程學系
    Keywords: 時脈與資料回復電路;四階脈波振幅調變;相位偵測器;抖動容忍度;Clock and data recovery;PAM-4;Phase detector;Jitter tolerance
    Date: 2019-08-19
    Issue Date: 2019-09-03 15:57:42 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 隨著串列傳輸系統對資料速率的需求逐漸提升,頻寬的需求也日漸嚴苛。四階脈波振幅調變技術可以應用於串列傳輸系統,其頻寬需求僅為非歸零式訊號的一半,因此系統可以操作在較低的頻率。然而,四階脈波振幅調變資料的多個電壓準位與複雜的資料轉態情形,將會提高時脈與資料回復電路的設計難度,因此,目前文獻設計上採用多組相位偵測器或是資料轉態選擇器,以達成較高的資料轉態密度或是較小的回復時脈抖動量。
    評估四階脈波振幅調變資料的特性對時脈與資料回復電路效能之影響,本論文提出一個應用於四階脈波振幅調變資料的二進位相位偵測器和還原資料選擇電路。所提出之四階脈波振幅調變資料相位偵測器,可用於偵測四階脈波振幅調變資料的各種邊緣型態,因此可增加資料轉態密度,進而獲得較佳的相位追鎖能力。論文中之設計亦使用還原資料選擇電路,以提升時脈與資料回復電路之抖動容忍度,並能降低誤碼率。避免因四階脈波振幅調變資料的急劇資料邊緣變化和多個電壓準位,造成高頻抖動容忍量下降。本論文之電路設計採用TSMC 40 nm (TN40G) 1P10M CMOS製程,操作電壓為0.9V,晶片面積為1.10 mm2,核心電路面積為0.11 mm2。輸入資料為10 Gb/s PRBS7 PAM-4時,佈局後模擬之還原時脈速率為5 GHz,還原時脈之峰對峰值20.8 pspp,方均根值3.21 psrms,功率消耗為41.6 mW。
    ;The demand of higher data rate in serial transmission is rising, and the bandwidth requirement is more critical. 4-level pulse amplitude modulation (PAM-4) technique can be adopted to decrease bandwidth requirement to half compared to NRZ data, so the clock in the receiver also can operate at lower frequency. However, the multiple levels and complicated transitions of PAM-4 data increase the design difficulty of clock and data recovery. Therefore, current papers use multiple phase detectors or data transition selector to achieve higher transition density or less recovered clock jitter.
    Considering the impact of characteristics of PAM-4 data on the performance of clock and data recovery. This thesis presents a bang-bang clock and data recovery with PAM-4 data phase detector and recovered data selection. The proposed PAM-4 bang-bang phase detector can be used on detecting all edge types of PAM-4 data. Therefore, the transition density can be increased, and then better phase tracking ability is acquired. This thesis also presents a recovered data selection circuit to enhance jitter tolerance of clock and data recovery, and is able to lower bit error rate. The circuit of this thesis is designed in 40 nm standard CMOS process with supply voltage of 0.9 V, the chip area is 1.10 mm2, the core area is 0.11 mm2. The post-layout simulation jitter of the recovered clock is 20.8 pspp and 3.21 psrm, and the total power consumption is 41.6 mW at 10 Gb/s PAM-4 27 – 1 pseudo random binary sequence (PRBS7) signal.
    Appears in Collections:[電機工程研究所] 博碩士論文

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