微波及毫米波切換器及四相位壓控振盪器整合除三 除頻器之研製;Design of Microwave and Millimeter-Wave Switches and Quadrature Voltage-Controlled Oscillator Integrated a Divide-by-Three Frequency Divider

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/81509

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81509

Title:	微波及毫米波切換器及四相位壓控振盪器整合除三除頻器之研製;Design of Microwave and Millimeter-Wave Switches and Quadrature Voltage-Controlled Oscillator Integrated a Divide-by-Three Frequency Divider
Authors:	劉浩恩;Liu, Hao-En
Contributors:	電機工程學系
Keywords:	砷化鎵;互補式金屬氧化物半導體;切換器;壓控振盪器;注入鎖定除頻器;次諧波注入鎖相迴路;GaAs;CMOS;Switch;VCO;ILFD;SILPLL
Date:	2019-08-19
Issue Date:	2019-09-03 15:58:02 (UTC+8)
Publisher:	國立中央大學
Abstract:	摘要隨著無線通訊快速的發展，半導體製程發展成熟及高速資料傳輸量的需求，許多系統已廣泛應用在微波與毫米波頻段上。在無線通訊系統中，高性能切換器為射頻前端的一個重要區塊。第一章本論文的緒論。第二章介紹數個射頻切換器及設計原理，分別採用行進波、分佈式及疊接式架構設計單刀單擲和單刀雙擲切換器並使用由穩懋半導體所提供 0.15 μm 及 0.1 μm GaAs 製程，其中單刀雙擲行進波切換器量測頻寬為 DC 至 36.5 GHz，插入損耗皆小於 3 dB，在目標頻率為 38 GHz 時插入損耗為 3.1 dB，隔離度為 39.34 dB；而單刀雙擲疊接式切換器量測，頻寬為 23 至 49 GHz，插入損耗皆小於 2 dB，在目標頻率為 39.3 GHz 時插入損耗為 1.47 dB，隔離度為 15.25 dB，輸入 1 dB 增益壓縮點高於 20 dBm。第三章藉由台積電 40 奈米 CMOS 製程，設計了 W 頻帶鎖相迴路之前端電路，並訂定了中心頻率為 94 GHz 的設計目標，實現次諧波注入鎖定四相位壓控振盪器整合注入鎖定除三除頻器之試製。振盪器量測的頻寬範圍為 93.28 到 97.37 GHz，可調頻寬為 4.1 GHz，輸出功率高於-22.4 dBm，距載波偏移 1-MHz 的相位雜訊約為 -80 dBc/Hz，而注入鎖定除頻器的輸出功率亦有在本章節量測完畢。此電路直流總功耗為 43 mW。第四章為整合應用於 Ka 頻帶之中性化寬頻功率放大器及具鎖相迴路自對準之次諧波注入鎖定壓控振盪器藉由台積電 90 奈米 CMOS 製程。量測的鎖頻範圍為 32.78 到 34.85 GHz，各個控制電壓的鎖定範圍約為 55 MHz，輸出功率高於 - 11.62 dBm，最低的距載波偏移 1-MHz 的相位雜訊為-106.3 dBc/Hz，抖動量積分範圍由 1 kHz 到 40 MHz 為 179 fs。整合注入鎖定鎖相迴路及功率放大器後的量測鎖頻範圍為 32.8 到 34.8 GHz，輸出功率高於 1.73 dBm。鎖相迴路直流總功耗為 68.15 mW。最後，第五章概括本論文所提出之研究成果，及可研究內容於毫米波前端收發機切換器子電路及在直接轉換的收發機系統中高頻四相位壓控振盪器，在未來的研究方向將集成射頻前端電路，未來的成果有望滿足收發器的實際應用。;Abstract With the rapid growth of wireless communication, the development of semiconductor processes and the demand for high-speed data transmission, numerous systems have been widely used in the microwave and millimeter-wave (MMW) bands. In wireless communication systems, high-performance switches are an important block in the radio frequency (RF) front end. Chapter 1 is the introduction of the thesis. Chapter 2 introduces several RF switches and the design principles for single-pole single-throw (SPST) and single-pole double-throw (SPDT) switches with travelingwave, distributed-type and stacked-FETs architectures. The switches are implemented using 0.15 μm and 0.1 μm GaAs processes provided by WIN Semiconductors. The SPDT traveling-wave switch has a measured bandwidth from DC to 36.5 GHz, an insertion loss of less than 3 dB, an insertion loss of 3.1 dB at a target frequency of 38 GHz, and an isolation of 39.34 dB. The stacked-FETs SPDT switch has a measured bandwidth from 23 to 49 GHz with an insertion loss of less than 2 dB and an insertion loss of 1.47 dB and an isolation of 15.25 dB at a target frequency of 39.3 GHz. The measured insertion loss degrades 1 dB (P1dB) is higher than 20 dBm. Chapter 3, a W-band phase-locked loop front-end is designed using the TSMC 40nm CMOS process, and the center frequency is 94 GHz. A sub-harmonically injection-locked quadrature voltage-controlled oscillator (QVCO) is integrated with an injection-locked divide-by-three frequency divider. The QVCO has a measured bandwidth from 93.28 to 97.37 GHz with a tuning range of 4.1 GHz, an output power of higher than -22.4 dBm, and a phase noise at 1-MHz offset of -80 dBc/Hz. In addition, the measured output powers of the injection-locked frequency divider also presented in this chapter. The total DC power consumption of the circuit is 43 mW. Chapter 4, a Ka-band integration of a neutralized wideband power amplifier (PA) and a sub-harmonically injection-locked phase-locked loop (SILPLL) is implemented using the TSMC 90 nm CMOS process. The measured SILPLL locking range is from 32.78 to 34.85 GHz, the locking range of each control voltage is about 55 MHz, the output power is higher than -11.62 dBm, and the minimum phase noise at 1-MHz offset is -106.3 dBc/Hz. The root mean square (RMS) jitter integrated from 1 kHz to 40 MHz is 179 fs. The integrated SILPLL and PA chip has a measured locking range from 32.8 to 34.8 GHz and an output power of higher than 1.73 dBm. The total DC power consumption of the circuit is 68.15 mW.X Finally, Chapter 5 summarizes the research results presented in this thesis, and the future works: sub-circuit in the millimeter-wave front-end transceiver switch and high frequency quadrature voltage-controlled oscillator in the direct conversion transceiver system. The research direction will be integrated RF front-end circuits, and the future results are expected to meet the practical application of the transceiver.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	164	View/Open

社群 sharing

Loading...