鐵電場效電晶體記憶體之穩定度及性能分析;Stability and Performance Analysis of Ferroelectric FET Based Memory

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Title:	鐵電場效電晶體記憶體之穩定度及性能分析;Stability and Performance Analysis of Ferroelectric FET Based Memory
Authors:	鄭哲安;Zheng, Zhe-An
Contributors:	電機工程學系
Keywords:	鐵電材料;鐵電鰭式場效電晶體;靜態隨機存取記憶體;負差動電阻;靜態雜訊邊限;輔助電路;感測放大電路;記憶體視窗;ferroelectric;ferroelectric FinFET (FE-FinFET);static random access memory;negative differential resistance;static noise margin;assist circuit;sensing amplifier;memory window
Date:	2019-09-26
Issue Date:	2020-01-07 14:37:37 (UTC+8)
Publisher:	國立中央大學
Abstract:	高效能與低功耗電晶體元件在記憶體電路上扮演重要的腳色，然而為了降低功耗，須降低其元件操作電壓(operating voltage)，使其導通電流(Ion)會隨著低電壓操作而下降，進而使電路穩定度下降，因此具有更低次臨界擺幅(subthreshold swing)、高導通電流及具有遲滯現象(hysteresis)特性的鐵電場效電晶體(Ferroelectric Field Effect Transistor, FEFET)，為提升記憶體穩定度的新興元件之一。本論文主要探討兩種不同形式之記憶體，第一種為利用Landau-Khalatnikov方程式結合Verilog-A模型與TCAD，分析在不同操作電壓下之鐵電鰭式場效電晶體靜態隨機存取記憶體單元(FE-FinFET SRAM cell)，第二種為利用Verilog-A模型與TCAD，分析單電晶體鐵電場效電晶體記憶體(1T-FEFET)之記憶體視窗(Memory window)，及元件參數變異對記憶體視窗的影響。在FE-FinFET SRAM cell之研究中，我們利用Table-lookup的方式模擬鐵電鰭式場效電晶體，並利用HSPICE進行靜態隨機存取記憶體電路分析，研究顯示在次臨界區(Subthreshold region)操作時，與FinFET SRAM cell相比，FE-FinFET SRAM cell有較佳的穩定度，其輔助電路對穩定度的改善也較顯著，同時在感測放大電路上具有更快的感測時間(Sensing time)。在穩定度分析中，由於鐵電鰭式場效電晶體獨特的負差動電阻特性(Negative differential resistance ;NDR)、更好的次臨界擺幅與導通電流，使FE-FinFET SRAM cell能夠解決在次臨界區操作時，讀取穩定度與寫入穩定度設計上的衝突，研究結果顯示跟FinFET SRAM相比，FE-FinFET SRAM cell在次臨界區操作時，同時提升了讀取穩定度與寫入穩定度。在靜態隨機存取記憶體性能分析部分，我們分析FE-FinFET SRAM cell之讀取存取時間(Cell read access time)與寫入時間(Time-to-write)，由於鐵電鰭式場效電晶體之導通電流較一般傳統電晶體大，因此在超臨界區(Superthreshold region)時，FE-FinFET SRAM cell讀取存取時間與寫入時間皆較FinFET SRAM cell快，但因鐵電鰭式場效電晶體之臨界電壓也較大，因此在次臨界區操作時，鐵電鰭式場效電晶體讀取存取時間與寫入時間皆較慢。在靜態隨機存取記憶體輔助電路與感測放大電路部分，由於在次臨界區有更顯著的負差動電阻特性，使得鐵電鰭式場效電晶體可同時改善讀取穩定度與寫入穩定度，同時鐵電鰭式場效電晶體不論在超臨界區或次臨界區，皆能夠比傳統電晶體有更快的感測時間。最後，我們分析單電晶體(1T)非揮發性鐵電場效電晶體記憶體的穩定度，透過電容阻抗模型與電晶體臨界電壓差之差異，我們分析不同的結構與材料參數對1T鐵電場效電晶體記憶體視窗(Memory window)之影響，調整鐵電層面積能夠更有效的優化記憶體視窗特性，增加記憶體耐久度。 ;High performance and low power consumption devices plays an important role in the memory circuit. However, the operating voltage of the device must be reduced for low power operation. As the operating voltage decreases, the on state current decreases, which degrades the stability of memory circuit. Therefore, ferroelectric FinFET (FE-FinFET) is one of the promising devices for low power applications due to its better subthreshold swing, high on-state current and non-volatile characteristics. In this dissertation, we explore two different types of memory circuits. First one is that we analyze the FE-FinFET static random access memory cell (FE-FinFET SRAM cell) at different operating voltage by using both TCAD and Landau-Khalatnikov (L-K) equation based Verilog-A model. Second, we analyze the memory window of the 1T ferroelectric FET(1T-FEFET) based non-volatile memory considering the impact of device parameter variations. For the FE-FinFET SRAM cell, we establish the table lookup model to simulate the FE-FinFET and use HSPICE to simulate the FE-FinFET SRAM cell. We propose that FE-FinFET SRAM cell shows better stability at subthreshold operation and shorter sensing time in sensing amplifier circuit. In stability analysis, due to negative differential resistance effect, better subthreshold swing and on-state current of FE-FinFET, FE-FinFET SRAM cell resolves the conflict between read and write operation at subthreshold region. In transient analysis of FE-FinFET SRAM cell, we analyze the cell read access time and time-to-write. Owing to the larger on-state current, FE-FinFET SRAM cell exhibits shorter cell read access time and time-to-write in superthreshold region. Due to larger threshold voltage, FE-FinFET SRAM cell shows slightly larger cell read access time and time-to-write in subthreshold region. With the strong negative differential resistance (NDR) effect in the subthreshold region, the assist circuit of FE-FinFET can improve the read and write stability simultaneously. The sensing amplifier circuit of FE-FinFET shows shorter sensing time than that of the conventional FinFET We analyze the 1T-FEFET memory. According to the capacitor impedance model and the current of the transistor, we show the influence of the different device parameter on the memory window of 1T-FEFET. Adjusting the area of ferroelectric layer shows the most significant impact on memory window. Therefore, adjusting the area ratio of ferroelectric layer to the interfacial layer can be used to improve the memory window and endurance.
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