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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81915


    Title: 考慮正確端口順序之階層式混合訊號電路架構辨識方法;On Hierarchical Structure Recognition Approach for Mixed-Signal Circuits with Accurate Port Orders
    Authors: 張祐愷;Chang, Yu-Kai
    Contributors: 電機工程學系
    Keywords: 架構辨識;混合訊號電路;Structure Recognition;Mixed-Signal Circuits
    Date: 2019-09-27
    Issue Date: 2020-01-07 14:37:42 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 隨著積體電路製程的演進,混合訊號系統的電路設計變得越來越複雜,如何加速類比與數位電路整合之後的模擬速度,是現在驗證系統晶片時不可或缺的環節。以硬體描述語言建立類比電路的行為模型,可以有效率的進行混合訊號系統的驗證,如果能透過自動化的方式將每個類比電路轉換成對應的行為模型,便可以大幅降低類比部分的模擬時間。因此,我們希望發展出一套有效率的電路架構分析流程,可以自動的從電路特徵或是接線關係中萃取出混合訊號電路中的構成區塊,並透過獨特的編碼方式快速準確的將電路中的數位和類比區塊辨識出來,自動替換成資料庫中所對應的行為模型。然而,在前人的論文中,數位電路分析部分的重複架構問題還未得到解決;類比電路分析部分也可能會出現區塊重疊的問題。因此本論文擴充原本的架構分析平台,在圖形同構的情況下加入額外的編碼,完善的解決數位電路架構辨識的漏洞,同時也能為電路的輸出入端口準確性最最後的驗證。在類比電路分析方面,重新編寫一個自下而上的階層式架構辨識方法,準確地決定出電路所屬的架構,解決重疊架構辨識的問題,並同時提高辨識結果的電路層級,如實驗結果所示,可以有效提升辨識結果的準確性,並且可以減少額外的系統驗證工作。;The design of analog/mixed-signal (AMS) integrated circuits is getting complex as technology advances. Speeding up the simulation involving with digital and analog circuits becomes a key to solve the system verification issues for SOC designs. Building their behavioral models for analog circuit blocks by hardware description language is an efficient approach for verifying AMS systems. If each analog circuit can be transformed into its corresponding behavioral model automatically, the simulation time for the analog part can be greatly reduced. Therefore, an efficient structure analysis flow is desired to automatically extract the building blocks, no matter it is an analog block or digital block, in a mixed-signal design based on the given circuit netlist. Using a special encoding scheme, the digital and analog blocks in the netlist can be identified quickly and replaced automatically by the corresponding behavior models built in the library. However, in previous works, different circuits may have duplicate structure in digital circuit analysis. In analog circuit analysis, the identified blocks may have overlap issues, too. In this thesis, we extend the previous structure analysis platform to consider these issues. In the case of duplicate structure, additional encoding is added in digital circuit analysis to verify the accuracy of the port orders of the circuit. In analog circuit analysis, a bottom-up hierarchical structure recognition approach is proposed to accurately determine which the circuit structure belongs to. This approach solves the structure overlap problem and raise the abstraction level of the identified models simultaneously. As shown in the experiments, the efficiency and accuracy of the identification results can be improved to reduce the extra efforts for system verification.
    Appears in Collections:[電機工程研究所] 博碩士論文

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