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    题名: 運用動態環切割來分析晶圓圖之特性;Wafer Map Characterization with Dynamic Ring Partition
    作者: 王嘉祺;Wang, Chia-Chi
    贡献者: 電機工程學系
    关键词: 晶圓圖;蝠翼模型;良率分析;Wafer map;Bat-wing models;Yield
    日期: 2020-03-13
    上传时间: 2020-06-05 17:40:29 (UTC+8)
    出版者: 國立中央大學
    摘要: 在製程變動的情況,晶片的良率會因為在晶圓上不同的位置下,會有不同的特徵,而隨著製程進入奈米的時代,所顯示的晶圓特徵圖案更加多樣。這些因製程而導致良率變化的瑕疵特徵圖案,從晶圓圖的觀點來觀察是最容易了解的。在以往的研究中,我們主要利用帕松分佈(Poisson distribution)模型來產生並分析均勻隨機瑕疵晶圓圖,而在本篇論文中,則是利用蝠翼模型(Bat-wing model)來產生非均勻隨機瑕疵晶圓圖,並計算每個故障晶粒與晶圓中心的距離,接著我們可以統計出故障晶粒對晶圓中心的距離平均值(DistanceMean)及標準差(DistanceSTD)。

    再來我們使用台積電所提供的實際晶圓:WM-811K晶圓資料庫去計算DistanceMean及DistanceSTD,利用這兩個參數來做為環切割的依據,將晶圓圖切割為外環(Out-Ring)、內環(Inner-Ring)、中心圓(Circle)三大區域,因每個晶圓圖的故障晶粒數、分佈情形皆不相同,因此切割出來的區域大小也不同。接著我們計算各個區域的故障晶粒比率及不良率,觀察這些參數的特性並用來輔助分類晶圓圖的九種錯誤樣態:Center、Donut、Scratch、Edge-Ring、Edge-Loc、Loc、Near-Full、Random、None。
    ;Under the process variation, the yield of the chips which are at the different locations with different characterization is in the same wafer. With the entry of the nanometer era, the wafer defect patterns become more various. The easiest way to observe these defect patterns due to process variation is from the viewpoint of the wafer map. In previous research, we use the Poisson distribution model to generate and analyze the homogeneous random defect wafer map. In this paper, we use the Bat-wing model to generate the nonhomogeneous random defect wafer map and calculate the distance between the wafer center and every bad die, then we can get the mean (DistanceMean) and the standard deviation (DistanceSTD) of the distance.

    Next, we use the actual wafer map data, which is the WM-811K wafer database released by TSMC to calculate DistanceMean and DistanceSTD. The ring partition is based on these two parameters. The wafer map is partitioned into three zones which are out-ring, inner-ring, and circle. The size of the three zones is dynamic due to the difference between the number and the distribution of bad die. Afterward, we calculate the ratio of the bad die and the defective rate of each zone. We analyze and use these parameters to help us classify the nine failure patterns which are Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-full, Random, none.
    显示于类别:[電機工程研究所] 博碩士論文

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