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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/84160


    題名: 應用於多使用者多輸入多輸出混合式波束合成系統之非均勻可調式特徵值解析器設計;Design of A Unified and Flexible Eigen-Solver for Hybrid Beamforming Algorithm in Multi-User MIMO Systems
    作者: 周書安;Su-An, Chou
    貢獻者: 電機工程學系
    關鍵詞: 波束合成
    日期: 2020-07-24
    上傳時間: 2020-09-02 18:25:00 (UTC+8)
    出版者: 國立中央大學
    摘要: 多使用者多輸入多輸出混合式波束合成系統為5G通訊的重要特色,由於此通訊系統的基站(base station)天線數量很高,因此在效能與運算複雜度之間折衷是多使用者多輸入多輸出系統能廣泛佈建的重要考量,需利用盡量少的資源消耗與運作成本來達成使用者所需的效能。
    本論文透過碼簿(codebook)配合階層式搜尋法(hierarchy search),減少波束搜尋(beam search)的時間複雜度,並比較各式碼簿配合搜尋法的效能與位元錯誤率(bit error rate)後,最後決定使用Discrete Fourier Transform (DFT)碼簿配合Multipath Decomposition and Recovery (MDR)搜尋法進行波束搜尋來實現射頻端的相移器設定,以避免射頻鏈(RF chain)數量過多,並且能夠擁有良好的效能及低位元錯誤率。
    特徵值解析器則於多使用者多輸入多輸出系統中扮演重要的角色,零特徵值之特徵向量可避免其他使用者的干擾(interference),而最大的特徵值之特徵向量可以確保訊號傳輸的過程中擁有最大的增益(gain)。本論文所提出的非均勻可調式特徵值解析器能夠令使用者調整參數,在計算複雜度與效能間得到適當的折衷效果。我們使用零特徵值模式設計發送端數位部分的前編器,並使用非零特徵值模式設計接收端的組合器(combiner)。本論文最後以40奈米製程實作非均勻可調式特徵值解析器之硬體。此硬體的處理器一可以支援 3×4 維度的輸入矩陣的零特徵值模式,而處理器二可以支援 5×5 維度的輸入矩陣運算非零特徵值模式吞吐量達到每秒5.26M (Mat per user/sec),gate count為472K,在時脈為5 ns,電壓為0.9 V的情況下,總功耗為215 mW
    ;Multi-user multiple input multiple output (MU-MIMO) hybrid beamforming is an important feature in 5G wireless communication systems. Because the number of transmit antennas at base station is large, the trade-off between performance and computational complexity is an important consideration.
    We use DFT codebook and hierarchy search based on multipath decomposition and recovery to reduce timing complexity for beam search to derive the proper settings of phase shifts. At the mobile station, the antenna weight vector is obtained from eigen-vectors with large eigenvalues to achieve good capacity.
    Eigen-solvers plays an important role in MU-MIMO system. The eigenvectors associated with the zero eigenvalues are needed since it can be used to get rid of the interference. On the other hand, the eigenvectors corresponding to the largest eigenvalues are often desired because they provide the subspaces with stronger gains. We propose a unified and flexible eigen-solver, which can reduce the computation complexity by adjusting the parameter for deflation. The digital precoders is realized by zero eigen-value mode, and the digital combiner is designed by non-zero eigen-value mode. Finally, the unified and flexible eigen-solver is implemented in CMOS 40nm technology. It can support 3×4 input matrix dimension in EVD processor 1 for zero-eigenvalue mode and 5×5 input matrix dimension in EVD processor 2 for non-zero eigen-value mode. The throughput is 5.26M (Mat per user/sec), and its gate count is 472K. The power consumption is 215mW at 0.9V and 200MHz operating frequency.
    顯示於類別:[電機工程研究所] 博碩士論文

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