| 摘要: | 近年來，物聯網(IoT)、人工智慧(AI)和5G行動網路的興起，帶動資料傳遞頻寬提升，然而，資料經過通道會受到符碼間干擾(Inter-symbol interference, ISI)影響，導致訊號完整度下降，因而帶動資料格式與補償電路的發展，相較於常見的不歸零式資料(Non-Return-to-Zero, NRZ)，四階脈波振幅調變(Pulse Amplitude Modulation 4, PAM-4)資料僅需較小傳輸頻寬的優點，使其獲得高速傳輸規格的青睞。另一方面，隨著通道衰減提升，等化器被廣泛應用於接收端以補償通道衰減，使其成為目前主流研究趨勢之一。
傳統決策回授等化器利用決策器判斷資料，並延遲適當時間消除資料位元週期長度的符碼間干擾，因為不能隨時改變其補償量的大小，只能針對資料或邊緣的符碼間干擾進行消除，故無法同時兼顧眼高和眼寬，本論文提出傳輸閘決策回授等化器(Transmission Gate Decision Feedback Equalizer, TG-DFE)，能夠在一個迴路裡同時補償資料和邊緣符碼間干擾，並且降低決策回授等化器因迴路延遲增加影響資料抖動的問題，搭配連續時間線性等化器(Continuous Time Linear Equalizer, CTLE)同時進行補償，利用自適應演算法針對臨界電壓、CTLE和TG-DFE的補償權重進行收斂，使等化器在不同通道衰減下都能正確的補償，此作法不僅降低硬體複雜度和功率消耗，也大幅提升等化器的使用彈性。
本論文使用TSMC 40 nm (TN40G) 1P10M之CMOS製程實現，電路操作電壓為0.9 V，輸入之資料速率為28 Gbps，輸入時脈為14 GHz。通道衰減範圍從12 dB到16 dB，在通道衰減12 dB時，等化後資料的峰對峰值抖動量為50.4 ps，方均根抖動量為14.7 ps；在通道衰減16 dB時，等化後資料的峰對峰值抖動量為51.6 ps，方均根抖動量為15.2 ps。在通道衰減16 dB時，整體功率消耗為95.9 mW，其中CTLE以及TG-DFE之等化器功率消耗為65.3 mW，自適應機制電路之功率消耗為30.6 mW，晶片面積為1.15 mm2，其中核心電路面積為0.09 mm2。
;In recent years, with the rise of Internet of Things (IoT), Artificial Intelligence (AI) and 5th generation mobile networks (5G), the bandwidth of data transmission has been increasing day by day. However, the signal integrity of high speed data gets worse after passing through the channel because of the inter-symbol interference (ISI). As a consequence, the data format and compensation circuits become popular. Morover, because the four level pulse amplitude modulation (PAM-4) data requires lower bandwidth, compared with non-return-to-zero (NRZ) data, it has been held in high regard by the high speed transmission protocols. On the other hand, the equalizer is used widely at receiver to compensate the attenuate signal, for the channel loss becomes higher and higher. Therefore, the equalizer turns into one of the mainstram research topic.
This thesis presents an innovative transmission gate decision feedback equalizer (TG-DFE) with data and edge ISI compensation. Both data and edge ISI can be eliminated simultaneously in one loop. With this architecture, the eye width of the data will have better immunity to the loop delay variation. This thesis implements continuous time linear equalizer (CTLE) and 1-tap TG-DFE to compensate the attenuate signal. Besides, this work includes the adaptive system which can optimize the threshold voltage (Vth) and the compensation of CTLE and TG-DFE. With the adaptive system, this circuit can work correctly under different channel loss. In this way, the complexity and power consumption of circuits are reduced, and the flexibility of adaptive equalizer is improved.
The fabricated chip was implemented by TSMC 40 nm (TN40G) 1P10M CMOS process. When the channel loss is 12 dB, the peak-to-peak jitter of equalized data is 50.4 ps and the root mean square (RMS) jitter is 14.7 ps. When channel loss is 16 dB, the peak-to-peak jitter of equalized data is 51.6 ps and the RMS jitter is 15.2 ps. The power consumption is 95.9 mW at a supply voltage of 0.9 V and the channel loss of 16 dB. The entire equalizer and the overall adaptative system utilize 65.3 mW and 30.6 mW of power, respectively. The chip area is 1.15 mm2 and the core area is 0.09 mm2. |
