本篇論文擬研究收發機中本地振盪源的相關電路，設計應用於第五代行動通訊(5th generation wireless systems)之n77、n79頻段本地振盪電路。本論文將先介紹振盪器中F類與反F類操作之優缺點，接著進行傳統電荷幫浦鎖相迴路與次取樣技術的分析，在鎖定的狀態下除頻器不會運作，因此不會貢獻相位雜訊至輸出端，此外由於缺少除N之路徑，相位頻率偵測器與電荷幫浦之雜訊不會被放大N 2倍，最後實現低功耗、低相位雜訊的次取樣鎖相迴路。論文一共實現三種電路，皆使用tsmcTM 0.18 μm互補式金氧半導體製程製作，內容如下所述： 低相位雜訊C頻段F類壓控振盪器 本電路實作具有低相位雜訊特性之F類控振盪器，使用變壓器耦合實作F類共振腔，並獨立主、副線圈中心抽頭偏壓以優化直流功耗。電路功耗為 8.7 - 10.3 mW，可調頻寬為 6.03 - 7.10 GHz (16.3%)，相位雜訊在 1-MHz 偏移頻率下最低為−121.86 dBc/Hz，達到 FoM最高為−187.5，晶片面積為 0.805\times0.961 mm2。 低相位雜訊S頻段反F類壓控振盪器 本電路實作具有低功耗、低相位雜訊特性之反F類控振盪器，使用變壓器耦合實作F類共振腔，並使用電流再利用技術以節省直流功耗。電路功耗為1.89 mW，可調頻寬為 3.196 - 3.608 GHz (12.1%)，相位雜訊在 1-MHz 偏移頻率下最低為−124.7 dBc/Hz，達到 FoM最高為−187.5，晶片面積為 0.805\times0.961 mm2。 利用F類壓控振盪器於C頻段次取樣鎖相迴路 本電路利用F類壓控振盪器，改善振盪器之相位雜訊，加入鎖頻迴路與次取樣迴路實現整數型C頻段次取樣鎖相迴路，於章節中完整介紹各子電路之用途及數學分析，整體電路功耗為28.2 mW，不含鎖頻迴路之功耗為10.2 mW，最後利用雜訊轉移函數計算整體系統之相位雜訊，晶片面積為1.023\ \times\ 1.283 mm2。 ;This thesis aims to design local oscillator (LO) circuits for the signal source of the fifth generation (5G) cellular communications in n77 and n79 band transceivers. In this thesis, we demonstrate the pros and cons between Class-F and Class-F-1 voltage control oscillator. It starts with classical charge-pump PLL (CPPLL) and sub-sampling PLL (SSPLL) system analysis. And the SSPLL is divider-less in the locked state, thus it will not contribute noise to the output. In addition, the analysis shows that the noises of PD and CP are not multiplied by N 2 to the output. Finally, a low power and low phase noise fully integrated 4.7 GHz SSPLL is implemented in 0.18-μm CMOS. A low phase noise C-band Class-F VCO Class-F oscillator has the features of high power efficiency and low phase noise. In this work, we use transformer coupling technique to realize Class-F LC-tank, and separate the center tape of the primary and secondary coils. The DC power consumption will be optimized to 8.7 - 10.3 mW. The measured tuning range is 6.03 - 7.10 GHz (16.3 %). The lowest phase noise at 1-MHz offset frequency is −121.86 dBc/Hz which is correspondent to the FoM of −187.5 dBc/Hz. The chip size includes all pads is 0.805\times0.961 mm2. A low phase noise S-band inverse-Class-F VCO The inverse-Class-F oscillator has the features of low power consumption and low phase noise. In this work, we use transformer coupling technique to realize inverse-Class-F LC-tank, and use current reuse technique to reduce the power consumption. The oscillator consumes the dc power of 1.89 mW. The measured tuning range is 3.196 - 3.608 GHz (12.1 %). The lowest phase noise at 1-MHz offset frequency is −124.7 dBc/Hz which is correspondent to the FoM of −187.5 dBc/Hz. The chip size includes all pads is 0.805\ \times\ 0.961 mm2. A C-band sub-sampling PLL with class-F voltage controlled oscillator The PLL adopted a Class-F VCO to improve the phase noise performance. Additionally, frequency-locked-loop and sub-sampling-loop are used to realize interger-N C-band SSPLL. This thesis analyzed the mathematical model of the CPPLL and SSPLL. And compare the noise contributions of each loop component. The PLL consumed the dc power of 28.2 mW. Without the FLL, the dc power is 10.2 mW. Finally, we calculate the overall phase noise of the system by noise transfer function. The chip size includes all pads is 1.023\ \times\ 1.283 mm2.
