運用於記憶體內運算的SRAM功率模型之研究;On SRAM Power Model for In Memory Computing

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題名:	運用於記憶體內運算的SRAM功率模型之研究;On SRAM Power Model for In Memory Computing
作者:	許元亨;Hsu, Yuan-Heng
貢獻者:	電機工程學系
關鍵詞:	記憶體;功耗估算;功耗模型;SRAM;power estimation;power model
日期:	2020-08-17
上傳時間:	2020-09-02 18:29:10 (UTC+8)
出版者:	國立中央大學
摘要:	隨著製程的進步，晶片尺寸不斷的縮小，晶片上的電晶體數量也越來越多。大大的增加了複雜晶片的設計難度。再加上現今許多先進的設計都被應用於低功率的設備，例如筆記型電腦，穿戴式設備…，延長高電晶體密度的電池壽命並且降低散熱設備變為設計中的重要考量。然而由於電路複雜度高，讓電晶體層級（transistor-level）的功耗估算變得十分複雜且耗時。因此，在電路設計階段時需要一個在高模擬層級的合適的耗模型來作功耗估算。為了支援記憶體內運算(In Memory Computing)的特殊記憶體，本篇論文提出一個高階功耗模型，不同於以往的功耗模型只能依據不同操作狀況來區分功耗，我們的功耗模型考慮了不同讀寫位址以及讀寫資料造成的影響，提供依據不同pattern對應的各種功耗。根據不同的操作模式，對讀取或寫入動作使用了不同的迴歸方法建構適當且準確的功耗模型。從實驗結果可以看出，不同操作中的功耗誤差率都在10%之內，且模擬時間大幅縮短。在將功耗模型和系統層級的模擬器Gem5結合後，透過一個簡單但完整的模擬測試也演示了支援系統層級模擬器的功能。 ;As the process continues to scaling, chip size is getting smaller, but the number of transistors on the chip is increasing. This significantly increases the difficulty for designing such complicated chips. In addition, due to the strong needs for low-power equipments, such as notebook computers, wearable devices, etc…, extending battery life and reducing heat dissipation become important considerations for such high-density designs. However, transistor-level power estimation becomes very complicated and slow for large designs. Therefore, proper high-level power modeling methods are required to evaluate the power consumption at design stages. In order to support the needs for In Memory Computing, this thesis proposes a high-level power consumption model for this special memory. Unlike traditional memory power models that can provide only the same value for different access, the proposed power model considers the effects of different address and data, and provides distinct power values for different input patterns. According to different operation modes, different regression approaches are proposed for memory read and write to construct accurate power models. According to the experimental results, the average error for different access modes can be controlled within 10%, and the simulation time is greatly reduced. After combing the proposed power model and the system –level simulator Gem5, a simple but complete program also demonstrates the capability to support high-level simulator.
顯示於類別:	[電機工程研究所] 博碩士論文

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