| 摘要: | 在現代通訊系統中為了因應高速資料傳輸量的需求，射頻的收發機系統之高頻寬的優勢也顯現出來，其中本地振盪源作為系統中升降頻的角色十分重要。而本地振盪源對相位雜訊的要求是非常嚴苛的，若是相位雜訊太差將會加到接收訊號上，會降低整體系統性能。本論文所提出鎖相迴路可準確提供穩定頻率，而注入鎖定技術可以有效降低相位雜訊，再搭配無除頻器架構來提升整體鎖定頻寬，來達到寬頻、低功耗、低相位雜訊、低抖動量之四相位振盪器。
第二章為X頻段多相位鎖相迴路，電路使用台積電0.18 μm互補式金屬氧化物半導體製程設計並實現，鎖相迴路包含考畢子壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器、兩級電流模式除頻器及四級單相位時序除頻器。此電路有迴路振盪之現象，但通過外接二階濾波器，使其有成功鎖定頻率，如何除錯將在本章說明。電路晶片面積1.06 × 0.8 mm2，模擬頻率範圍為9.3 GHz至10.8 GHz，而量測頻率範圍為9.49 GHz至9.52 GHz，輸出功率約為-3 dBm，相位雜訊在1 MHz頻率偏移時為-96 dBc/Hz，電路直流總功耗為60.4 mW。此外在本章還探討迴路頻寬對於鎖相迴路之相位雜訊的影響。
第三章採用具有低相位雜訊低抖動優勢的鎖頻迴路架構，首先介紹次諧波注入鎖定技術，通過使用變壓器耦合的架構，可使得注入鎖定振盪器擁有更好的特性。本次設計之鎖頻迴路並無除頻器，使得整體架構較為簡單且達到低直流功耗的效果，在研製過程中使用理論計算線性模型，進行模擬分析鎖頻迴路的穩定度以及相位雜訊與抖動量的評估，來藉此優化整體相位雜訊及抖動量。電路實現於台積電65 nm CMOS製程，晶片面積為1 × 0.7 mm2，量測鎖定頻率範圍為30 GHz至36.6 GHz，輸出功率平均約為-9 dBm，相位雜訊在1 MHz頻率偏移時為-130.3 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz為8.7 fs，四相位誤差及振幅誤差分別為0.9˚及0.43 dB，電路直流總功耗為31.3 mW。
第四章介紹無除頻器頻率追蹤迴路之W頻段次諧波注入鎖定四相位壓控振盪器，首先介紹理論模型及轉移函數，接著利用ADS(advance design system)軟體進行模擬分析鎖頻迴路，能夠有效率的分析鎖頻迴路系統的開迴路及閉迴路響應。此外，利用線性模型分析比較各種結構頻率合成器之相位雜訊及抖動量。電路實現於台積電 40 nm CMOS製程，晶片面積為0.982 × 0.86 mm2，模擬振盪器頻率範圍為91.6 GHz至96.7 GHz，量測振盪器頻率範圍為98.2 GHz至102.6 GHz，注入鎖定振盪器距載波偏移1 MHz的相位雜訊為-93.3 dBc/Hz。頻率相較模擬往高頻嚴重偏移，將會在本章節除錯。
;In modern communication systems, in order to meet the demand for high data rate wireless communication the advantage of the high operating bandwidth of the radio frequency (RF) transceiver system is also apparent. The local oscillator (LO) source is very important as the role of upconversion/downconversion in the system. One challenge facing such systems is the strict phase-noise requirements of the local oscillator (LO). The LO phase noise adds directly to the received signal and results in limited overall system performance. The phase-locked loop (PLL) proposed in this paper can accurately provide a stable frequency. The injection locking technology can be employed to effectively reduce the phase noise. The total locking range is enhanced with a divider-less architecture to achieve a quadrature oscillator with wide locking range, low power consumption, low phase noise, and low jitter.
The Chapter 2 is the X-band multi-phase phase-locked loop. The PLL is using TSMC 0.18 μm CMOS process design and implementation. The building blocks of the presented PLL is composed of a QVCO, a phase-frequency detector, a charge pump, a loop filter and two-stage common-mode logic dividers and four-stage true single-phase clocking dividers. This circuit has the phenomenon of loop oscillation, but through the external second-order filter, it has a successful locking frequency. The debug for the proposed PLL is also presented in this chapter with the simulated results. The chip size is 1.06 × 0.8 mm2. The simulated frequency is 9.3 GHz to 10.8 GHz. The measured frequency is from 9.49 GHz to 9.52 GHz. The output power is close to -3 dBm. The measured phase noise is -96 dBc/Hz at 1-MHz offset. The total DC power consumption is 60.4 mW. In addition, the effect of loop bandwidth is also addressed to improve the phase noise of the PLL.
In Chapter 3, a subharmonic-injection locked frequency-locked loop with the advantages of low phase noise and low jitter is adopted. The subharmonic-injection locking technology is introduced. By using the transformer coupling architecture, the injection locking oscillator has better performance. The frequency locking loop is designed using divider-less loop, the overall phase noise and jitter can be properly designed using the presented linear model of the frequency-locked loop, and the design of the presented subharmonic-injection frequency locking loop is completely presented with the simulated results to further reduce the output phase noise and jitter. The circuit is designed using TSMC 65 nm CMOS process, the chip size is 1 × 0.7 mm2. The measured overall frequency locking range is from 30 GHz to 36.6 GHz. The average output power is about -9 dBm. The phase noise is -130.3 dBc/Hz at 1-MHz offset. The RMS jitter (integrated from 1 kHz to 40 MHz) is 8.7 fs. The phase error and amplitude error are 0.9˚ and 0.43 dB, respectively, and the total DC power consumption is 31.3 mW.
In Chapter 4, we introduce the W-band subharmonic injection locked quadrature VCO with divider-less frequency tracking loop. First, we introduce the theoretical model and transfer function. Then we use ADS (advance design system) software to simulate and analyze the frequency locking loop, which can effectively analyze the open loop and closed loop response of the frequency locking loop system. In addition, the theoretical model is used to analyze and compare the phase noise and jitter of various structure frequency synthesizers. The circuit is using TSMC 40 nm CMOS process. The chip size is 0.982 × 0.86 mm2. The simulated VCO frequency is 91.6 GHz to 96.7 GHz. The measured VCO frequency is 98.2 GHz to 102.6 GHz. The phase noise is - 93.3 dBc/Hz at 1-MHz offset. If the frequency is seriously offset from the analog to the high frequency, it will be debugged in this chapter. |
