本論文研究是以高電子遷移率之砷化銦鎵和高電洞遷移率之鍺作為通道材料，開發互補式金屬-氧化物-半導體場效電晶體(CMOS FETs)，並整合於低成本且易量產之矽基板上。此研究採用選擇性磊晶方式，使用有機金屬化學蒸氣沉積系統於鍺奈米溝槽中依序成長砷化鋁銦緩衝層與砷化銦鎵通道層。研究結果顯示，砷化鋁銦在高溫成長之沉積速率較慢且易形成島狀形貌；若以先低溫再高溫的二階段成長方式，則可獲得連續性較佳之磊晶形貌。 本研究亦以原子層沉積系統沉積氮化鋁/氧化鋁雙層結構作為鍺與砷化銦鎵共閘極高界電係數材料，採用快速熱氧化和 HF 浸泡進行沉積前表面處理，探討不同退火溫度下之金氧半界面特性。在氮氣環境下以350℃退火兩分鐘，鍺與砷化銦鎵金氧半電容以電導法萃取之界面捕陷密度(Dit)分別為3.59×1011eV-1cm-2和5.29×1011eV-1cm-2。在沉積閘極金屬TiN與歐姆金屬Ti/AlSiCu後，在氮氣95%和氫氣5%的環境中以350℃退火五分鐘，鍺電容Dit可降至1.95×1011eV-1cm-2，100 kHz下之遲滯電壓偏移∆VFB從0.13V降至0.078V；砷化銦鎵電容Dit降至4.79×1011eV-1cm-2，遲滯電壓偏移從0.18V降低至0.056V，表示此退火條件有效降低界面缺陷。 結合N型通道磊晶設計以及共閘極製程，砷化銦鎵FinFET在Wfin=50nm 與Lg=60nm最大電流密度為0.29μA/μm、S.S為558mV/dec以及Ion/Ioff ratio為1.35×10^2，閘極漏電密度大約為10^-6 μA/μm。接著透過後製程的方式，蝕刻元件下方的鍺塊材以減少漏電流路徑，SS可下降至394mV/dec.且Ion/Ioff ratio 則可提升至4.35×10^2。鍺FinFET亦透過相同的蝕刻方式，每減少1μm2面積的鍺塊材可下降約18.5µA漏電流，亦證實通道下方鍺塊材為造成元件漏電的主要路徑之一。;This study aims at fabricating a hybrid complementary metal-oxide-semiconductor (CMOS) structure consisting of high electron mobility InGaAs and high hole mobility Ge channels on Si substrates. The heterogeneous integration is implemented by selective area epitaxy of InGaAs channel and an InAlAs buffer on nano-patterned Ge templates by metal-organic chemical vapor deposition (MOCVD). This shows that the growth rate of the InAlAs buffer at high temperature is lower than that at low temperature and tend to form islands on the surface. Surface morphology is significantly improved by using a two-step growth method, i.e the growth is performed at low temperature and followed by high temperature growth. A common gate-stack process for both InGaAs and Ge channels is developed in this work. AlN/Al2O3/InGaAs and AlN/Al2O3/Ge MOS capacitors (MOSCAPs) are fabricated for investigating the interfacial characteristics. Rapid thermal oxidation (RTO) followed by dipping the samples in HF solution is used for surface treatment. The post-deposition annealing temperature is optimized based on their capacitance-voltage characteristics. The Ge and InGaAs MOSCAPs annealed in N2 ambient at 350 ℃ for two minutes exhibit an interface trap density of 3.59×1011eV-1cm-2 and 5.29×1011 eV-1cm-2, respectively. The interface trap density canbe further reduced by 45% and 10% for Ge and InGaAs MOSCAPs respectively after post-metal gate (TiN) annealing (PMA) at 350 ℃ for five minutes. In addition, the ∆VFB decreases from 0.13 V to 0.078 V for Ge MOSCAPs and 0.18 V to 0.056 V for InGaAs MOSCAPs. Combining the epitaxial growth and common gate processes, InGaAs FinFETs with Lg/Wfin of 80 nm/120 nm exhibit a maximum drain current of 0.29 µA/µm, a subthreshold swing of 558 mV/dec, and an Ion/Ioff ratio of 1.35×10^2. The gate leakage current is well below 10^-6 µA/µm. After removing the Ge layer under the InGaAs channel, the subthreshold swing of the InGaAs FinFETs decreases from 558 mV/dec to 394 mV/dec with an increase in Ion/Ioff ratio from 1.35×102 to 4.35×10^2 . A similar trend has also been observed on Ge FinFETs, indicating the Ge bulk layer under the channel is the main leakage current path in these devices.
