| 摘要: | 本篇論文研究主題為疊接式功率放大器設計與雙閘極功率放大器設計，疊接式功率放大器電路同時使用砷化鎵(GaAs)基板之異質接面雙載子電晶體(HBT)與高電子遷移率電晶體(HEMT)組合而成，包含完整的分析模擬與實驗結果，經由探討兩層疊接式功率放大器之最佳組合，進一步討論至三層疊接式功率放大器之最佳組合，論文中分析了不同方式的疊接架構(HEMT-HBT, HBT-HEMT, HBT-HBT, 與 HEMT-HEMT疊接架構)，分析最佳的兩層疊接架構方式而得到較大的輸出阻抗，進而提升最大輸出功率以及寬頻的特性，此單晶片單級兩層疊接式功率放大器具有操作頻率由3.5至6.5 GHz增益大於13 dB，P1dB大於26.4 dBm，效率可達38%特性，並以兩層疊接式架構為基礎，探討三層疊接架構中之第三層疊接電晶體對於整體三層疊接式功率放大器電路的增益、頻寬以及輸出功率特性的影響，並有效提升三層疊接式功率放大器電路的輸出功率與效率特性，此單晶片單級三層疊接式功率放大器具有操作頻率由3.1至5.8 GHz增益大於15 dB，P1dB大於29.5 dBm，最大效率可達38.3%特性。
雙閘極功率放大器使用砷化鎵(GaAs)基板之高電子遷移率電晶體(HEMT)組合而成，雙閘極電晶體佈局中的汲極(Drain)端與源極(Source)端之間有兩個閘極(Gate)控制通道特性，基於小訊號萃取技術得到雙閘極電晶體等校電路模型，並根據疊接式功率放大器設計分析方式，設計並分析使用雙閘級高電子遷移率電晶體功率放大器，分析兩種不同架構(空乏-空乏型D-D mode, 與增強-增強型E-E mode)之雙閘極功率放大器，使用E-E mode雙閘極電晶體架構設計之功率放大器具有較大的1-dB輸出功率壓縮點，較好的線性度與寬頻特性，此單晶片單級雙閘極功率放大器具有操作頻率由3.6至8 GHz增益大於12 dB，P1dB大於26.8 dBm，最大效率可達29.7%特性。
本論文藉由疊接式功率放大器設計方式，成功設計了兩層疊接式功率放大器、三層疊接式功率放大器與雙閘極功率放大器，其中分析了疊接式電晶體設計對於頻寬的影響以及設計於雙閘極功率放大器得到較好的線性度特性，未來可進一步應用於新世代無線通訊功率放大器。;Research on the stacked power amplifiers (PAs) and dual-gate PAs in microwave are presented in this dissertation. The stacked power amplifier circuits are designed using several heterojunction bipolar transistor (HBT) and high electron mobility transistor (HEMT) process. The analysis and simulation is agreed well with experimental results. By investigated the best combination of transistors in dual stacked power amplifier, the best stacked transistor of triple stacked power amplifiers is analyzed. Different stacked architectures (HEMT-HBT, HBT-HEMT, HBT-HBT, and HEMT-HEMT stacking architectures) are analyzed, and the optimal dual stacked architecture is analyzed to obtain larger output impedance, enhancement in the maximum output power, and broad bandwidth characteristics. The single-chip single-stage dual stacked power amplifier achieves an operating frequency from 3.5 to 6.5 GHz with a gain of more than 13 dB, an output 1-dB compression point (P1dB) of higher than 26.4 dBm, and an efficiency of up to 38%. Base on the architecture of the proposed dual stacked PA, the third-stacked transistor in the triple stacked PA is analyzed and realized with an enhancement of gain, bandwidth and output power performance. The single-chip single-stage triple-stacked power amplifier achieves an operating frequency from 3.1 to 5.8 GHz with a gain of more than 15 dB, a P1dB of higher than 29.5 dBm, and a maximum efficiency of up to 38.3%.
The dual-gate power amplifier is realized by a GaAs HEMT process. There are two gates between the drain and source terminal in one transistor. The channel is controlled by two gates in different operation mode. The equivalent model of dual-gate transistor is obtained from the small signal extraction. By using of the equivalent model and the design methodology of stacked PA, two dual-gate PAs are designed and realized. According to the design and analysis of dual-gate PA, two different architectures (depletion-depletion D-D mode, and enhancement-enhancement E-E mode) are realized. The dual-gate E-E mode PA exhibits a larger output P1dB, a good linearity and broad bandwidth characteristics. The single-chip single-stage dual-gate power amplifier achieves an operating frequency from 3.6 to 8 GHz with a gain of more than 12 dB, a P1dB greater than 26.8 dBm, and a maximum efficiency of up to 29.7%.
Dual stacked PAs, triple stacked PAs and dual-gate PAs are successfully designed and analyzed in this dissertation. The bandwidth characteristic is analyzed by the stacked transistor. According to the design methodology of the stacked PA, the dual-gate PAs are designed and analyzed with good linearity characteristic. It can be further utilized to the new generation wireless communication PA and modern mobile application due to its good circuit performance and the mass-production MMIC process. |
