| 摘要: | Ka頻段有不少重要應用，例如在28 GHz與39 GHz頻段的第五代行動通訊與在35 GHz的雲雷達。無論在第五代行動通訊或雷達等應用中，相位陣列都扮演重要角色。在相位陣列中，相位偏移器則是不可或缺的組件。在本論文中，我們採用傳輸線基全通網路架構，並使用TSMC 0.18-μm CMOS製程實現操作於35 GHz的四位元與五位元數位式相位偏移器。在電路中，我們引入交叉耦合對來產生負轉導，以補償被動元件所造成的損耗。
在第二章中，首先介紹傳輸線基全通網路架構及其設計公式的推導。次節介紹互補式交叉耦合對之等效電路，最後以模擬結果驗證引入交叉耦合對確實能降低全通相移器的植入損耗。
在第三章中，我們以前述的具損耗補償之傳輸線基全通網路來設計一個四位元相位偏移器。其中，22.5°、45°及90°相移級採用全差動式傳輸線基全通網路架構，180°相移級採用一對單刀雙擲開關來實現；晶片面積為1×2 mm2。模擬結果顯示，在26.7 GHz 至38.8 GHz（36.9%頻寬），均方根相位誤差小於2°，振幅誤差在±1 dB內，植入損耗低於11.7 dB。量測結果顯示，所有狀態的相移量皆有變大，造成均方根相位誤差變大至22.5°；在Ka頻段內植入損耗僅低於24.8 dB，與模擬結果相差甚多。在此設計，電路中的交叉耦合對應該在所有狀態下皆有同樣的直流電流通過；但在量測時，我們發現交叉耦合對只有在on state有電流，而在off states沒有電流。交叉耦合對未正確工作是植入損耗變大很多的可能原因。此外，經重新模擬，我們發現交叉耦合對也可能有多出原先未預期的寄生電容，因而造成相位誤差的增加。
在第四章中，我們採用相同的傳輸線基全通網路架構設計一個五位元相位偏移器；設計流程與前章相同，差異在於使用較低的系統阻抗及傳輸線特徵阻抗，期望傳輸線造成的損耗可以較低。模擬結果顯示，在33.0 GHz 至39.4 GHz（17.7%頻寬），均方根相位誤差小於3°，振幅誤差在±0.85 dB內，植入損耗低於14.1 dB。然而，量測結果顯示，相移量偏差甚多，均方根相位誤差變差至102.5°，而植入損耗在Ka頻段亦僅低於56.0 dB。在量測時，我們同樣發現交叉耦合對並未正確工作。經重新模擬後，發現加入寄生元件於交叉耦合對中，可使響應於低頻與量測結果較為貼合。但不幸地，量測結果與模擬結果相差甚多的確切原因仍未找到。
本論文成功設計了使用具損耗補償之傳輸線基全通網路的全差動式數位式相位偏移器；然而量測結果與模擬結果相差甚多。經過重新模擬，已經可以推知造成此差異的部分原因。;There are quite a few notable applications in Ka band, such as the fifth-generation (5G) mobile communications at 28 GHz and 39 GHz and the cloud radar at 35 GHz. In both 5G communication and radar applications, phased arrays play important roles. Phase shifters are indispensable components in a phased array. In this thesis, 35-GHz 4-bit and 5-bit digital phase shifters are designed by adopting transmission-line-based all-pass network topology and implemented using TSMC 0.18-μm CMOS process. Moreover, cross-coupled pairs are incorporated in the phase shifter design to provide negative transconductance and thereby compensate the loss resulting from the passive components.
In Chapter 2, transmission-line-based all-pass network is introduced and its design equations are derived. Next, the equivalent circuit for complementary cross-coupled pair is introduced. Finally, simulations are performed to verify that, by incorporating cross-coupled pair, the insertion loss of the all-pass phase shifter could indeed be lowered.
In Chapter 3, a 4-bit phase shifter is designed using the aforementioned transmission-line-based all-pass network with loss compensation. The 22.5°, 45°, and 90° phase-shifting stages assume the topology of fully-differential transmission-line-based all-pass network, whereas 180° phase-shifting stage is realized by a pair of SPDT switches. The chip area is 1×2 mm2. Simulation results show that, between 26.7 GHz and 38.8 GHz (36.9% bandwidth), the RMS phase error is less than 2°, the amplitude error is within ±1 dB, and the insertion loss is less than 11.7 dB. However, measurement results show that, for all 16 states, the phase shifts are larger than expected, causing the RMS phase error to deteriorate to 22.5°, and the insertion loss is only less than 24.8 dB within Ka band, which differs a lot from the simulation results. In this design, the cross-coupled pairs in the circuits should consume constant amount of DC current regardless of the phase-shifting states. However, during measurement, it is found that there is DC current flowing through the cross-coupled pair only when the phase shifting stage is in on state. In other words, the cross-coupled pairs did not function correctly, which may be one possible reason why the insertion loss increases so much. Moreover, after re-simulation, it is found that there may be additional parasitic capacitance in parallel with the cross-coupled pair, which is responsible for the increase of phase errors.
In Chapter 4, a 5-bit phase shifter is designed by adopting the same transmission-line-based all-pass network topology with the same design procedure, except that lower system impedance and characteristic impedance are used, hoping that the loss of the transmission lines may be lower. Simulation results show that, between 33.0 GHz and 39.4 GHz (17.7% bandwidth), the RMS phase error is less than 3°, the amplitude error is within ±0.85 dB, and the insertion loss is less than 14.1 dB. However, measurement results show that the phase shifts deviate a lot, leading to a deteriorated RMS phase error of 102.5°, and the insertion loss is only less than 56.0 dB within Ka band. During measurement, it is also found that the cross-coupled pairs in this circuit did not function correctly, either. After re-simulation, the simulated results could fit the measured results at low frequencies by adding parasitic components to the cross-coupled pairs. But unfortunately, actual cause for the large discrepancy between the simulated and measured results has yet to be found.
In this thesis, fully-differential digital phase shifters are successfully designed using transmission-line-based all-pass network with loss compensation. However, large discrepancies between the measured and simulated results are observed. Nonetheless, after re-simulations, part of the reasons for the large discrepancy has been proposed. |
