應用於IEEE 802.3bp?-2016車用乙太網路收發機之等化器、回音消除器與時序回復電路設計與整合;Design and Integration of Equalizer, Echo Canceller and Timing Recovery Circuit for IEEE 802.3bp?-2016 Automotive Ethernet Transceiver

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题名:	應用於IEEE 802.3bp?-2016車用乙太網路收發機之等化器、回音消除器與時序回復電路設計與整合;Design and Integration of Equalizer, Echo Canceller and Timing Recovery Circuit for IEEE 802.3bp?-2016 Automotive Ethernet Transceiver
作者:	陳衍祐;Chen, Yen-Yu
贡献者:	電機工程學系
关键词:	車用乙太網路;通道等化器;回音消除器;時序回復電路;automotive ethernet;channel qualizer;echo canceller;timing recovery
日期:	2021-01-22
上传时间:	2021-03-18 17:39:50 (UTC+8)
出版者:	國立中央大學
摘要:	隨著行車安全、自動駕駛以及各項行車產品電子化的蓬勃發展，實時AI影像辨識及各項設備間的訊號傳輸需求越來越受重視。本論文依據IEEE 802.3bp?-2016規範標準[1]，設計出車用Gigabit乙太網?傳輸之?位基頻收發機晶片。本論文針對?用乙太網路的環境開發專屬的數位濾波器演算法，著重在通道等化器、回音消除器以及時序回復電路（Timing Recovery Circuit）之演算法及數位電路設計。由於有線車用乙太網路通道屬於擴散通道，因此在等化器演算法採用改良後之較低複雜度的定值模數演算法（Constant Modulus Algorithm, CMA）及決策導向（Decision Directed, DD）演算法來克服通道效應。通道等化器包含前饋等化器（Feedforward Equalizer, FFE）及決策回饋等化器（Decision Feedback Equalizer, DFE），分別用?消除針對前符碼間的干擾及後符碼間的干擾。由於單一雙絞線全雙工傳輸的回音干擾現象，經由演算法推導及模擬結果分析回音消除器之必要性，因而系統更加設計了數位回音消除器。時序回復電路用來克服時脈不匹配效應，透過採用穆勒與姆勒演算法(Mueller and Muller, M&M)的相位檢測方法，加上改良後的可適性消除等化器(Adaptive Canceler Equalizer, ACE)，使得的相位檢測器獲得的通道資訊更接近理想通道響應sinc function。關於硬體實現，先使用Verilog HDL描述與模擬，透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，最後經由Design Compiler與IC Compiler來驗證在製程為TSMC-40nm下之電路功能。;Due to the vigorous development of autonomous vehicles, driving safety and various electrical automotive products, real-time AI image recognition and signal transmission between devices have become increasingly important. This thesis will present the algorithms and circuits for channel equalization, echo cancellation, and timing recovery to develop an IEEE 802.3bp?-2016 compatible next generation gigabit Ethernet digital baseband transceiver dedicated to an automotive environment. Harmful Inter-Symbol Interference (ISI) will be mitigated by the use of a feedforward equalizer and a decision feedback equalizer, which will deal with the pre-cursor and post-cursor of ISI respectively. At first, the Modified Constant Modulus Algorithm (MCMA) is employed at feedforward equalizer due to the lower complexity, and after the preliminary converge the Decision-Directed algorithm will be applied to both the feedforward equalizer and the decision feedback equalizer. To account for the physical layer specifications of point-to-point full duplex 1 Gb/s Ethernet operations over single balanced twisted-pair copper cables, this system is also designed to include a digital echo canceller. The necessity of the echo canceller is analyzed through algorithm derivation and simulation results. In the part of timing recovery circuit, Phase-Lock Loop (PLL) with the Mueller and M?ller algorithm is used to overcome the clock mismatch effect between AD/DA converters. Furthermore, the improved adaptive cancellation equalizer (ACE) is adopted so that the channel information obtained by the phase detector is closer to the ideal channel response. The hardware is simulated through Verilog HDL. The function is then verified by using SMIMS VeriEnterprise Xilinx FPGA, and implemented in the process of TSMC-40nm through Design Compiler and IC Compiler.
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