三維接地式四面體網格之矩陣係數驗證與半導體元件模擬;3D grounded cube element and matrix coefficient verification and its applications to semiconductor device simulation

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題名:	三維接地式四面體網格之矩陣係數驗證與半導體元件模擬;3D grounded cube element and matrix coefficient verification and its applications to semiconductor device simulation
作者:	陳彥伯;Chen, Yen-Po
貢獻者:	電機工程學系
關鍵詞:	半導體元件;三維半導體元件模擬;元件模型化;等效電路模型;有限元素分析法;牛頓拉福森法;semiconductor device;3D semiconductor device simulation;device modeling;equivalent circuit model;finite element method;Newton-?Raphson method
日期:	2021-07-13
上傳時間:	2021-12-07 13:01:12 (UTC+8)
出版者:	國立中央大學
摘要:	本篇論文主要是利用牛頓拉弗森方法跟元件掃描法開發一個全新的接地式等效電路模型，再由此電路建立矩陣係數驗證之方法並進行半導體元件之模擬。由前面的研究者之工作可知，計算時常常會因程式中的錯誤而導致最後計算數據的嚴重失真，故為了要有效的提升程式的除錯效率，我們開發了矩陣係數驗證法。根據我們的計算，若是該驗證法能夠成功將可大幅的提升我們後續計算數據的準確性。而在我們所開發的這套接地型等效電路模型中，重新強化了程式的可讀性，在進行矩陣係數驗證法時也能進行更簡潔且有效率的計算。在此計算中，我們也發現：當使用接地型等效電路時，雖然模擬所需時間長會有些微的增加，但是對驗證的效率有顯著的提升，而對模擬的?值?會有影響。當係數驗證法成功後，我們嚐試模擬半導體元件，在這個部份我們將使用三維四面體串接以構成半導體之結構來進行模擬。模擬的元件則包含了串接電阻、PN junction、NPN transistor、MOS capacitor等元件，最後我們也會針對各元件的特性曲線圖去做模擬數據精準度之探討，都有令人滿意的結果。 ;This thesis mainly uses the Newton Raphson method and the element by element method to develop a new grounded equivalent circuit model, and then establishes the method of matrix coefficient verification from the circuit and simulates the semiconductor devices. From the work of the previous researchers, it is known that errors in the calculation often result in serious distortion of the final calculation data. Therefore, in order to effectively improve the debugging efficiency of the program, we have developed a matrix coefficient verification method. According to our calculations, if the verification method is successful, it will greatly improve the accuracy of our subsequent calculation data. In the grounded equivalent circuit model we developed, the readability of the program has been re-enhanced, and it can also perform more concise and efficient calculations when performing the matrix coefficient verification method. In this calculation, we also found that when the grounded equivalent circuit is used, the time required for the simulation will increase slightly, but it will significantly improve the efficiency of verification without affecting the calculated value. When the coefficient verification method is successful, we try to simulate the semiconductor devices. In this part, we will use the three-dimensional tetrahedron series connection to form the semiconductor structure for simulation. The simulated devices include series resistor, PN junction, NPN transistor, MOS capacitor. Finally, we will discuss the accuracy of the simulated data according to the characteristic curve of each devices, and all have satisfactory results.
顯示於類別:	[電機工程研究所] 博碩士論文

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