在晶圓製造及封測廠產線中，每天都會有大量的晶圓被產出及測試，而在產線機台運作中，常會因為機台發生問題而去影響到晶圓的良率，而工程師們可以藉由經過製造或測試機台所產生出來的晶圓瑕疵圖之錯誤特徵來判斷是哪道製程有問題，找出根本原因，並針對不同的根本原因（Root cause analysis）對機台去做調整，以提升良率，例如：在晶圓針測（Chip probing）中可能會因為測試探針上沾黏一些物質，導致測試探針無法順利地接觸待測晶粒之Pad，測試資料（Test pattern）無法順利輸入到電路當中，導致測試結果為壞品，可能不符合真實情況，因此有這樣問題的晶圓需要進行重測（Retest）動作，將一些被測試機判為壞品但其實是好品的晶粒分辨出來，以提升良率，在傳統方法上主要是以人工的方式做判別，增加工程師負擔，為了減輕工程師的工作量以及加速問題的排除，我們希望能以自動化的方式實現一套辨識系統。我們主要是以深度學習的方式，針對晶圓瑕疵圖辨識及分析，我們提出無樣態先的二階段辨識模型，將資料集當中數量級距差太多的類別獨立成另一階段處理，並以實際製程資料做為依據來評估我們的模型，基於我們二階段的模型下，總體資料的辨識率平均能達到92%，運算時間約12ms/wafer。;In the production line of wafer manufacturing, packaging and testing process, many wafer maps are produced and tested. Many problems occur and impact yield. Yield engineers may judge defect patterns of wafers to find problems with production line and find root causes. Then, other engineers according to root cause and adjust machines to avoid new defects are generated. In the chip probing process, probing needle may not appropriately contact resistance because of particle on the tip of needle, for example. That may cause test pattern cannot input circuit under test. This problem can be resolved by retesting and changing probing needle. The above method can revise the judgment of test result of the good die from function fail to function work. In traditional, these works are finished by human being. However, if we can build an automation recognition tool, it will reduce loading with yield engineers. In this thesis, we focused on wafer map failure pattern recognition and based on deep learning algorithm. We proposed None-First Two-Stage model to improve recognition accuracy on WM-811K dataset. This method is applicable to the imbalance quantity of different failure type of dataset. We divided all processes into two stages. The first stage recognizes larger number of failure type and the second stage classifies all failure types. We also evaluate our method by real-world wafer map dataset. Consequently, we measured recognition accuracy and average accuracy could achieve 92.12%. Computation time cost could achieve 12 ms/wafer.
