本論文之實驗晶片使用TSMC 40 nm (TN40G) 1P10M CMOS製程設計，電路操作電壓為0.9 V，輸入資料為20 Gb/s四階脈波振幅調變訊號，並利用PRBS7進行編碼，還原時脈速率為5.0 GHz，還原時脈之抖動峰對峰值為8.93 pspp，方均根植為1.49 psrms，抖動容忍度於佈局前模擬中與傳統二進位相位偵測器相比則有15.63 %的改善，功率消耗為122.84 mW，晶片面積為0.96 mm2，核心電路面積為0.096 mm2。;In recent years, with the rapid development of technology, the demand for transmission rate is increasing. High Speed Serial Link Technology has replaced the parallel transmission and become the mainstream transmission technology, such as HDMI、Displayport、USB、SATA and PCI-Express. In addition, as data rates continue to increase, PAM-4 data is being used to replace NRZ data in order to reduce the bandwidth requirements of the system to meet higher data rate.
This thesis refers to the CEI-28G-VSR specification and presents a half rate PAM-4 clock and data recovery (CDR) with data independent phase tracking compensation technique. The proposed phase tracking compensation phase detector (PTCPD) solves the problem that the conventional bang-bang phase detector (BBPD) may reduce the high frequency jitter tolerance (JTOL) when the input data has long run situation. In addition, by removing the re-timing circuit of the BBPD to reduce the loop latency, the JTOL can be improved. In order to transmit the PAM-4 signal, this thesis presents a threshold voltage adaptive system. This system will adaptively converge the reference levels of the PAM-4 signal. Then, the resistors are used to divide the appropriate threshold voltage for the CDR to detect the PAM-4 signal. With this adaptive system, the PAM-4 CDR can achieve greater flexibility in use.
This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process with 0.9 V supply voltage and the data rate is 20 Gb/s PRBS7 PAM-4 signal. The recovered clock is 5.0 GHz. The simulated jitter of the recovered clock is 8.93 pspp and 1.19 psrms. In pre-layout simulation, 15.63% improvement in jitter tolerance compared to conventional BBPD. The total power consumption is 122.84 mW, chip area is 0.96 mm2 and the core area is 0.096 mm2.
