中大機構典藏-NCU Institutional Repository-提供博碩士論文、考古題、期刊論文、研究計畫等下載:Item 987654321/86903
English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 80990/80990 (100%)
造訪人次 : 41663199      線上人數 : 1721
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋


    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/86903


    題名: 砷化鎵異質整合及矽基毫米波輻射計接收機暨氮化鎵功率放大器之研製;Design of Radiometer Receiver Using GaAs & CMOS Process and Power Amplifier Using GaN Process
    作者: 賴仕豪;Lai, Shih-hao
    貢獻者: 電機工程學系
    關鍵詞: 輻射計接收機;降頻器;功率放大器;radiometer receiver;mixer;power amplifier
    日期: 2021-10-25
    上傳時間: 2021-12-07 13:24:45 (UTC+8)
    出版者: 國立中央大學
    摘要: 本論文主要研究為砷化鎵異質整合輻射計接收機、矽基降頻器與氮化鎵功率放大器。其中,輻射計接收機包括三個子電路,分別為切換器、低雜訊放大器與功率偵測器。
    第二章提出一個使用穩懋0.15 μm GaAs-PIN HEMT製程操作於Ka頻段單刀雙擲切換器,為於接收機最前端,作為切換接收天線訊號或者雜訊源校正用途。切換器後方之電路為低雜訊放大器,可以提升整體輻射計接收機之響應度與降低雜訊等校功率,使用串接三級源極退化電感架構實現。輻射計接收機之最後端為功率偵測器,採用差動對輸入架構實現,此架構之優點為提供更高的響應度,由於功率偵測器需要差動訊號輸入,因此前級設計一個主動式平衡不平衡轉換器。整體輻射計接收機之在33 GHz有最大響應度為1.2 MV/W、最小雜訊等效功率為10 fW/√Hz,工作頻寬為2.8 GHz,總晶片面積為3×1 mm2。
    第三章提出一個使用台積電90 nm CMOS製程操作於W頻段之降頻器,採用達靈頓混頻單元與本地振盪源閘極饋入之電路架構,並且於降頻器之輸入端設計馬相平衡不平衡轉換器,針對馬相平衡不平衡轉換器之耦合線長度差以及補償線長度作設計與分析,目的為提升本地振盪埠至射頻埠之隔離度。當降頻器給定本地振盪功率為5 dBm之轉換增益為-12.5 dB,射頻埠頻寬為75至115 GHz,本地振盪埠之射頻埠隔離度在60 GHz為36 dB,雜訊指數為18 dB,整體功耗為2.6 mW,整體晶片面積為0.88×0.73 mm2。
    第四章提出一個使用穩懋0.15 μm GaN製程操作於Ka頻段之功率放大器,高輸出功率與高線性度之功率放大器於發射機為關鍵電路,本章使用傳輸線進行功率整合,並且同時達到寬頻的效果。本功率放大器之小訊號增益為10.6 dB,輸出1dB增益壓縮點為17.1 dBm,飽和輸出功率為21 dBm,輸出三階截斷點為27 dBm,總晶片面積為3×1.4 mm2。
    於論文的最後,第五章為本論文之總結與未來研究發展方向。
    ;In this thesis, a radiometer receiver based on gallium arsenide (GaAs) high-electron-mobility transistor (HEMT) process, a W-band down-conversion mixer using CMOS process and a high-power amplifier using gallium nitride (GaN) process are presented. The radiometer receiver includes three blocks, single-pole double-throw (SPDT) switch, low noise amplifier, and power detector.
    In Chapter two, a SPDT switch is presented using 0.15-μm GaAs-PIN HEMT process provided by WIN Semiconductors corporation. The SPDT switch at the front-end of the radiometer receiver can be used to switch signal from antenna or calibrate using noise source. The following circuit after SPDT switch is a low noise amplifier (LNA) which can dramatically increase radiometer’s responsivity and largely decrease noise equivalent power. The LNA is realized using three-stage source degeneration architecture. At the output of the radiometer receiver is a power detector which is designed using differential signal input architecture. Since the power detector needs a differential signal input, an active balanced-to-unbalanced circuit is employed. The radiometer receiver achieves a maximum responsivity of 1.2 MV/W and a minimum noise equivalent power of 10 fW/√Hz at 33 GHz. The operation frequency bandwidth is 2.8 GHz. The total chip size of the radiometer receiver is 3×1 mm2.
    In Chapter three, a W-band down-conversion mixer is realized using TSMC 90 nm process. To achieve wide operation frequency, a Darlington-mixing cell with LO source-pumped architecture is chosen and to enhance isolation from LO port to RF port, a Marchand Balun is also designed. The length of the compensated line and couple line in Marchand Balun are further analyzed and discussed in this chapter. While the LO power is 5 dBm, the mixer achieves a conversion gain of -12.5 dB. The RF port frequency bandwidth is from 75 to 115 GHz. The isolation from LO port to RF port is 36 dB at 60 GHz. The noise figure is 18 dB with a total dc power consumption of 2.6 mW. The chip size of the down-conversion mixer is 0.88×0.73 mm2.
    In Chapter four, a Ka-band power amplifier (PA) is realized using WIN Semiconductors corporation 0.15 μm GaN process. In modern transmitter system, high output power and high linearity PA plays an important role. To combine four transistor output power and achieve wide bandwidth at the same time, a wide transmission line is utilized in this power amplifier. The proposed PA achieves a small-signal gain of 10.1 dB, an output 1-dB compression power of 17.1 dBm, an output saturated power of 21 dBm, and an OIP3 of 27 dBm. The total chip size of the power amplifier is 3×1.4 mm2.
    In final chapter, conclusions and future works are presented.
    顯示於類別:[電機工程研究所] 博碩士論文

    文件中的檔案:

    檔案 描述 大小格式瀏覽次數
    index.html0KbHTML124檢視/開啟


    在NCUIR中所有的資料項目都受到原著作權保護.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明