具共用方塊無偏移技術之2.4 GHz類比式 雙迴路校正倍頻延遲鎖相迴路;2.4 GHz Analog Dual Loop Calibration Multiplying Delay Locked Loop with Block-Sharing Offset-Free Technology

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Title:	具共用方塊無偏移技術之2.4 GHz類比式雙迴路校正倍頻延遲鎖相迴路;2.4 GHz Analog Dual Loop Calibration Multiplying Delay Locked Loop with Block-Sharing Offset-Free Technology
Authors:	黃大祐;Huang, Ta-Yu
Contributors:	電機工程學系
Keywords:	倍頻延遲鎖定迴路;Multiplying Delay Locked Loop
Date:	2022-01-21
Issue Date:	2022-07-14 00:23:51 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文提出以無除頻器與類比式為架構的2.4 GHz具有雙迴路校正的倍頻延遲鎖相迴路，並且使用共用方塊無偏移技術來校正因週期性注入而產生的參考突波和定量性抖動。在倍頻延遲鎖相迴路上，週期性注入參考輸入時脈，以重置相位且消除累積抖動，並且使得迴路頻寬等效變大，有助於壓制振盪器的高頻雜訊，但因週期性注入參考時脈的行為，導致定量性抖動與參考突波的產生。在校正參考突波的方面，本篇使用延遲線迴路儲存振盪週期之週期時間，並且使用共用方塊無偏移技術，將不同時間點的振盪週期與注入週期作比較並精準調整振盪器頻率，以達到週期之間相等並降低參考突波。由於使用共用方塊無偏移技術，使得電路上的偏移會因為共用而被互相消除，以提升降低參考突波的效果。本論文使用90 nm 1P9M (TN90GUTM)之CMOS製程來實現，電路操作電壓為1 V，參考輸入時脈頻率為50 MHz，高頻輸出時脈頻率為2.4 GHz。以下為佈局後模擬的數據，沒有校正時脈之參考突波為-24.2 dBc，經過校正時脈之參考突波為-54.5 dBc，因此有效降低30.3 dBc的參考突波，時脈之峰對峰值抖動量10.3 ps，方均根值抖動量為1.7 ps，振盪器的相位雜訊在1 MHz條件下為-92.6 dBc/Hz，經過倍頻延遲鎖相迴路的輸出相位雜訊降至-116.7 dBc/Hz，積分之方均根抖動量為0.4 ps，且功率消耗為6.58 mW，晶片面積為1.28 mm2，核心電路面積為0.057 mm2。 ;A 2.4 GHz multiplying delay locked loop with dual-loop calibration based on no divider and analog structure is presented in this thesis. And use the block-sharing offset-free technology to calibrate the reference spur and deterministic jitter caused by periodic injection. In the multiplying delay locked loop, the reference input clock is periodically injected to reset the phase error and eliminate the accumulated jitter, and make the loop bandwidth equivalently larger, which helps to suppress the high-frequency noise of the oscillator. However, the behavior of periodic injection can cause deterministic jitter and reference spur. In terms of calibrating reference spur, this article uses a delay line loop to store the cycle time of the oscillation cycle. By using the block-sharing offset-free technology, the oscillation period and the injection period at different time points are compared at the same time. And accurately adjust the oscillator frequency to achieve equal cycle between periods and reduce the reference spur. As a result of the block-sharing offset-free technology, the offset of the circuit will cancel each other without affecting the calibration result. Thereby improving the effect of reducing the reference spur. The proposed multiplying delay locked loop is manufactured using TSMC 90nm 1P9M CMOS process. The power supply voltage is 1 V, the input reference frequency is 50 MHz, and the operating frequency is 2.4 GHz. The following is the simulation result after layout. The uncalibrated reference spur of the clock is -24.2 dBc, and the reference spur of the calibrated clock is -54.5 dBc. Therefore, the reference spur is reduced by 30.3 dBc. The peak-to-peak jitter of the clock is 10.3 ps, and the root-mean-square jitter is 1.7 ps. The phase noise of the oscillator is equal to -92.6 dBc/Hz at a frequency offset of 1 MHz. The output phase noise after the multiplying delay lock loop is reduced to -116.7 dBc/Hz. The integrated root-mean-square jitter is 0.4 ps, and the power consumption is 6.58 mW. The full chip area is 1.28 mm2 and the core area is 0.057 mm2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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