IEEE Std 802.3bz™-2016標準中所採用的低密度同位元檢查矩陣有區塊平行特性，此矩陣被設計給(6,32)-regular (2048,1723) Reed Solomon-based Gallager-LDPC code，使得我們可以在相同位元錯誤率(BER)之下採用部分平行化設計減少面積以及繞線複雜度。 本篇論文中，提出了一個適用於™-2016標準的低密度奇偶檢查碼之解碼器，使用正規化最小和演算法(Normalized Min-Sum Algorithm)與0.5的正規化因子(scaling factor)來實現，如此一來電路不需要使用到任何一顆乘法器，並利用標準中所採用的3842048奇偶檢查矩陣(parity-check matrix)，將矩陣分解成6個642048的子矩陣，使解碼平行化。除了矩陣分解外，再將檢查點位置提取出來做接線，矩陣大小再度降低為6個6432的子矩陣，同時使用上述兩種方法可以大大降低晶片面積大小。另外因為解碼平行化的關係，兩次迭代解碼時間將平均分散在4096個時脈中，如此可以大大降低晶片功耗。 最後我們使用TSMC 40nm製程操作在680MHz最高傳輸率可以達到9.157Gbps的吞吐量。實作後電壓供應0.9伏特時平均功率消耗為 153 mW，解碼器核心面積大約是 4 mm2。 ;A grouped-parallel low-density parity check (LDPC) matrix in standard for IEEE Std 802.3bz™-2016 is demonstrated for a (6,32)-regular (2048,1723) Reed Solomon-based Gallager-LDPC code. It is adopted to reduce the hardware area cost and routing congestion with similar bit error rate (BER). In this thesis, we propose a LDPC decoder in standard for IEEE Std 802.3bz™-2016 by using Normalized Min-Sum Algorithm with scaling factor equal to 0.5. The 3842048 parity-check matrix can be partitioned into 6 groups of 642048 submatrix in standard. In addition to matrix partitioning, the submatrix can be resized to six 6432 if we only use 1s in parity-check matrix for routing. Both of these two methods are used, we can significantly reduce the chip area. Also, lower power consumption if we use two times iteration decoding by timesharing in 4096 clock cycle time. Finally, the implementation of decoder with TSMC 40nm process can achieves a decoding throughput 9.157Gb/s under the maximum clock frequency of 680Mhz. The average power consumption is close to 153 mW and the core size is approximately 4 mm2.
